Register bypassing in an asynchronous superscalar processor
Davies, S.J.; Elston, C.J.; Findlay, P.
Citation: Davies , S J , Elston , C J & Findlay , P 1999 , Register bypassing in an asynchronous superscalar processor . UH Computer Science Technical Report , vol. 328 , University of Hertfordshire .
Register bypassing, universally provided in synchronous processors, is more difficult to implement in an asynchronous design. Asynchronous bypassing requires synchronization between the forwarding and receiving units, with the danger that the advantages of synchronization operation may be nullified by reintroducing the lock-step operation of synchronous processors. We present a novel implementation of register bypassing in an asynchronous processor architecture. Our technique of Decoupled Operand Forwarding provides centralized control over the bypassing operation, yet allows multiple execution units to function asynchronously. Our ideas are presented within the context of the development of Hades, a generic asynchronous processor architecture. We employ single-issue and dual-issue simulations of Hades to quantify the benefits of Decoupled Operand Forwarding and conclude that Decoupled Operand Forwarding yields significant speedups because of its success in removing register files from the critical timing path.