Received: 13 November 2020 Revised: 15 February 2021 Accepted: 4 March 2021 IET Power Electronics
DOI: 10.1049/pel2.12116
ORIGINAL RESEARCH PAPER
A novel resonant ZVS power converter with self-driven
synchronous rectifier for low-voltage high-current applications
Najmehossadat Nourieh Yichuang Sun Oluyomi Simpson
School of Physics, Engineering and Computer
Science (SPECS), University of Hertfordshire,
Hatfield, UK
Correspondence
NajmehossadatNourieh, School of Physics, Engi-
neering andComputer Science (SPECS),University
ofHertfordshire,HatfieldAL10 9AB,UK.
Email: n.nourieh@herts.ac.uk
Abstract
This paper presents a novel isolated resonant zero-voltage switching converter with a self-
driven synchronous rectifier for low-voltage high-current applications. The active resonant
tank comprises of a transformer leakage inductance, a capacitor and a diode-connected
MOSFET which provides zero-voltage switching conditions for all switches. Due to the
use of leakage inductance of the transformer in both the primary and secondary sides, the
resonant tank and the output section require no external inductor, resulting in a major size
reduction of the circuit. The proposed converter has the advantages of high efficiency; low
switching, conducting, and thermal losses; high switching frequency range and isolation;
and small size. To verify the proposed converter, a laboratory prototype was manufactured
with satisfactory performance. The practical results show that the power efficiencies of the
converter including self-driven synchronous rectifier for the light load and the full load are
91.9% and 94.95% at output power Pout = 20 W and Pout = 100 W, respectively.
1 INTRODUCTION
Enhancing power density and efficiency are the main require-
ments of a modern power supply. Soft-switching techniques are
developed to reduce switching losses. At zero-voltage switching
(ZVS) conditions, not only is the switch voltage-current overlap
eliminated, but also the turn-on losses created due to the MOS-
FET output capacitance (Coss) and reverse recovery of the PN
junctions are removed properly [1, 2]. In resonant converters,
passive LC circuits are adopted to provide soft switching con-
ditions. In ZVS resonant converters, the switching frequency is
increased significantly while the switching, conducting and ther-
mal losses are kept low suitably. Therefore, an ZVS resonant
converter is one of the best candidates for a modern power
supply [3, 4].
An ever increasing demand is the requirement of off-line
low-voltage high-current power supply for electronics loads [5,
6]. Synchronous rectifiers (SR) present much lower conduc-
tion losses than the conventional PN/Schottky rectifying diodes
[7]. For the SR MOSFETs, the required gate signals should be
generated synchronously with the converter DC/AC section
[8–10].
This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is
properly cited.
© 2021 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology
The traditional methods use integrated circuits (IC) and self-
driven synchronous rectifiers (SDSR). A major problem is the
short-circuit condition occurring at the transition intervals cre-
ated due to reverse-recovery of the PN junctions and the trans-
former secondary side leakage inductance [11, 12]. Employing
current-doubler can intensify this problem [13, 14]. To obvi-
ate it, employing current sensors are suggested at the cost of
increasing the converter cost and complexity [15]. In the SDSR,
the gate signals are generated directly by the transformer aux-
iliary windings [16, 17]. Compared with gate driving meth-
ods which are using ICs, SDSR decreases the design complex-
ity, production cost, elements number, and gate driving loss
[18–20]. A problem is the malfunction of SDSR in converters
using dead time to regulate output voltage. This happens as,
within dead-time intervals, the induced voltage on the auxiliary
winding is reduced and consequently the SR may not be driven
properly [21].
Integration of ZVS condition and SR is a challenging topic in
many researches for different applications [22, 23]. In [12], SR
is adopted with asymmetrical half-bridge converter where the
output voltage polarity is used to generate gate signals. How-
ever, a large inductor should be used after the rectifiers. Another
IET Power Electron. 2021;1–12. wileyonlinelibrary.com/iet-pel 1
2 NOURIEH ET AL.
similar work is presented in [24] where a cascade synchronous
boost ZVS converter is introduced. Literature [14] integrated a
half-bridge converter with SR and current-doubler. Here, ZVS
operation is not achieved for all switches and a DC-block capac-
itor should be used in this regard. In [25, 26], the converter core
comprised a series-resonant converter and a four-diode full-
wave rectifier used at the transformer secondary side, but only
two diodes are SR. The other variant with complicated control
and operation is proposed in [27].
This paper presents a converter which benefits from zero-
voltage switching, resonance, isolation, integrated transformer
and self-driven synchronous rectifier for low-voltage high-
current applications. Profiting from advantages of high effi-
ciency; low switching, conducting, and thermal losses; low EMI
(electromagnetic interference) and gate driver loss; small size;
and high switching frequency range and isolation, this converter
can be applied in various applications such as domestic elec-
tronic appliances, LED power sources, battery charging pur-
poses, inductively heated appliances, wireless power charging
of portable electronics, transcutaneous power transfer systems,
biomedical implants, photovoltaic power optimizer, telecom,
and other centralized modular and distributed power applica-
tions [3, 5, 8, 12]. Furthermore, low-voltage high-current power
electronic converters have received huge interest of both indus-
try and academia for their application in stand-alone electric
power generating systems. After introducing the operation of
the converter, a comparison between three versions of this con-
verter including the converter with simple diode-base rectifier,
the converter with SDSR, and the one with diode-connected
MOSFET in resonant tank and SDSR in rectification section, is
given.
The transformer leakage inductance in conjunction with a
resonant capacitor and a diode-connected MOSFET called Qr
form an active resonant network (tank) showing a remarkable
difference of the proposed converter from LLC [28]. Thereby,
the transformer leakage inductance reflected on the transformer
primary side is not problematic, as it is used as a resonant induc-
tor. The employed active resonant tank decreases switching-
frequency deviation over the whole range of load variations as
well as provides ZVS operation for all switches [25, 27]. The
mechanism of this converter, due to its active resonant tank,
drastically limits the switching frequency variations to appro-
priate small values (typically, 10% variations from zero-load to
full-load). Thus, components can be designed optimally. A self-
driven synchronous rectifier with center-tapped transformer is
employed at the transformer secondary side. The output section
does not need any additional inductor; therefore, the converter
size is greatly reduced. Theoretical analysis and experimental
verifications are presented in detail in the following sections to
verify the proposed converter.
The paper is organized as follows: Section 2 provides infor-
mation about our proposed converter and its operation inter-
vals. In Section 3, we further discuss self-driven synchronous
rectifier. Section 4 describes experimental results while Sec-
tions 5 and 6 discuss the analysis of power loss and concludes
the paper respectively. Finally, in the Appendix, ZVS analysis is
presented.
FIGURE 1 Proposed resonant ZVS converter
2 PROPOSED CONVERTER
The proposed converter is presented in Figure 1 and its opera-
tion intervals are illustrated in Figure 2. The converter has seven
operation intervals in case of using diode rectifier [29] and 10 in
case of using SDSR as shown in Figure 3. The switches Q1 and
Q2 constitute an inverter leg. The capacitors C1 and C2 (with
the MOSFET parasitic output capacitance Coss) are set in paral-
lel with the switches to provide ZVS condition at class D [1, 3].
An active resonant tank including Lr, Cr, and Qr is employed.
The resonant inductor Lr can be the sum of the transformer
primary leakage inductance and an external inductor. TheMOS-
FET Qr stabilizes the converter operation. Its junction capaci-
tance is absorbed by Cr; therefore, its reverse-recovery time is
not problematic. The switches SR1 and SR2 are the output syn-
chronous rectifiers driven by the transformer auxiliary windings.
It is assumed that the converter is in the steady state, all the
circuit elements are ideal, and the output capacitor Co is large
enough to keep the output voltage constant during one switch-
ing cycle. In Equations (1)–(3), we define various parameters
which will be used in the following discussion: The parameters
α and β are used to simplify the equations and B is the con-
verter normalized voltage gain "B = nA = nVo/Vs. Shown in
Figure 2, φ1 and φ2 are the conduction angles of Q1 and Q2,
respectively. In each operation interval, Inumber = ir(tnumber). In
addition, the parasitic inductance is also used as resonant induc-
tance since its total value is around nH, which will be added to
the 25 μH resonant inductance.
𝜔r = 2𝜋 fr =
2𝜋
Tr
=
1√
LrCr
, Ro =
n2Vo
2
Pout
, (1)
B = n
Vo
VS
= nA, Zr =
√
Lr
Cr
, (2)
𝛼 =
Cr
C1 +C2
, 𝛽 =
1 + 𝛼
𝛼
, 𝜔𝛼 =
√
1 + 𝛼𝜔r . (3)
Mode 1 (t0 < t < t1): Prior to t0, the diode d1 was conduct-
ing and the gate signal for Q1 has been set. Therefore, at t0, the
NOURIEH ET AL. 3
FIGURE 2 Key waveforms of the proposed converter
Q1 is turned on under the ZVS condition. The voltage of the
resonant capacitor (called resonant voltage vr) is zero at t0. Due
to Lr, vr starts increasing in a resonant fashion when Q1 con-
ducts. Then, a positive voltage applies on the primary side of
the transformer which reflects to the secondary and auxiliary
windings (which provide gate voltage signal for SR1). Then, the
switch SR1 is turned on and power is delivered to the output.
t1 − t0 = T1, T1 =
𝜙1
𝜔r
, (4)
vr (t ) =VS (1 − B)
[
1 − cos(𝜔r (t − t0))
]
, (5)
ir (t ) =
VS
Zr
[
(1 − B) sin(𝜔r (t − t0))
]
. (6)
Mode 2 (t1 < t < t2): By reaching vr to the voltage of the
input source (VS), the voltage across the primary winding is
reduced. Therefore, the auxiliary voltage applied on the gate of
SR1 is also decreased to less than the threshold voltage which
causes the MOSFET to turn off.
However, due to the transformer leakage inductance at the
secondary side, LSS2, the anti-parallel diode of SR1 remains ON
and continues the current. At the end of this mode,Q1 is turned
off. Due to C1, Q1 is turned off at ZVS condition. According to
Figure 2, durations of this mode along with the previous mode,
in which Q1 is conducting, is defined as φ1/ωr. To provide the
phase lag needed to maintain ZVS turn-off, ir should be positive
at t2, or in other words φ1 < 180. All equations of this mode are
identical to those of the previous interval.
Mode 3 (t2 < t < t3): Since t2 is prior to the zero-crossing
instant of the resonant current, ir, by turning Q1 off at t2, the
remaining current of Lr flows through C1 and C2. Then, the
middle voltage (the voltage of node M in Figure 1 which is
denoted by vM), is reduced to zero through a resonant with Lr
at t3.
ir (t )
Vs∕Zr
=
(1 − B) cos𝜙1√
1 + 𝛼
sin(𝜔𝛼 (t − t1))
+ (1 − B) sin𝜙1 cos(𝜔𝛼 (t − t1)) (7)
vr (t )
Vs
=
(1 − B) cos𝜙1√
1 + 𝛼
sin(𝜔𝛼 (t − t1))
−
(1 − B) sin𝜙1
1 + 𝛼
cos(𝜔𝛼 (t − t1)). (8)
Mode 4 (t3 < t< t4): At t3, the diode d2 is forward biased and
ir flows through it until t4, when the resonant current ir becomes
zero. The auxiliary winding of the transformer applies a positive
voltage on the gate of SR2 and turns it on. During this mode, the
gate signal for Q2 is set which leads to turning on MOSFET at
ZVS. At the time of t3, the current of Ir is called I3 which is used
in Equation (10). Here, it should bementioned thatφ(t4 < t< t5)
and φ(t5 < t < t6) are called φx1 and φx2, respectively. Consider-
ing
−B
sin𝜙2
= 𝛾, the equations are as below.
ir (t )
Vs∕Zr
= (2B−𝛾)sin(𝜔r(t − t3)), (9)
vr (t )
Vs
=Vs[I3sin(𝜔r(t − t3)) + B], (10)
𝜙x1 + 𝜙x2 = 𝜙d . (11)
Mode 5 (t4 < t < t5): At t4, the current of Q2 becomes
positive, then the MOSFET of Q2 conducts. Due to the trans-
former secondary side leakage inductance LSS2, the diode d3
remains ON until t5, when the current of LSS2 is reversed and
d3 is turned OFF at ZCS condition. During this mode, the
energy stored in Cr is transferred to the output, but vr is still
positive at t5.
ir (t )
Vs∕Zr
= (2B − 𝛾) sin (𝜔r (t − t4)), (12)
vr (t )
Vs
= −(2B − 𝛾) cos (𝜔r (t − t4)) + B. (13)
4 NOURIEH ET AL.
VS VSVS
Vs
VsVsVS
Vs
VsVs
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
C1
C2
SR1
SR2
SR1
SR2
SR1
SR2
SR1
SR2
SR1
SR2
SR1
SR2
SR1
SR2
SR1
SR2
SR1
SR2
SR1
SR2
Qr Qr
Qr
Qr
Qr
Qr
Qr Qr Qr
Qr
Cr Cr Cr
CrCr Cr
Cr
Cr
Cr
Cr
d1
d2
d1
d2
d1
d2
d1
d2
d1
d2
d1
d2
d1
d2
d1
d2
d1
d2
Lr Lr Lr
Lr
Lr Lr
Lr
Lr Lr
Lr
Vo Vo
Vo
Vo
Vo
VoVo
Vo
(a) (b) (c)
(d) (e)
(f)
(g)
(h)
(i)
(j)
d1
d2
Vo
Q1
Q2
Vo
FIGURE 3 Schematic circuit of the proposed high efficiency isolated resonant using a self-driven synchronous rectifier
Mode 6 (t5 < t < t6): During this mode, remaining energy
stored in Cr is transferred to the output until vr reaches zero at
t6. Shown in Figure 2, the interval from t4 to t6 is defined as φd,
which indicates the conduction angle of Qr.
ir (t )
Vs∕Zr
= (2B − 𝛾)
[
−
(cos𝜙x2)
(sin𝜙x1)
cos(𝜔r(t − t5))
+ [cos(𝜔r(t − t5))]+
(sin𝜙x2 cot𝜙x1)
Cr
+
cos𝜙x2
C r
]
,
(14)
T5 + T6 =
𝜙d
𝜔r
, 𝜙d = cos
−1
(
B
2B − 𝛾
)
, (15)
vr (t )
Vs
= (2B − 𝛾)
[
(cos𝜙x2)
(sin𝜙x1)
sin(𝜔r(t − t5)) + cos(𝜔r(t − t5))
]
.
(16)
Mode 7 (t6 < t < t7): By setting vr to zero at t6, the diode-
connected MOSFET Qr is forward biased at ZVS. Then the
resonant current ir continues through it and the voltage of vr
is clamped at zero. During this mode, the magnetic energy
stored in Lr is transferred to the output and the magnitude of ir
decreases linearly.
ir (t )
Vs∕Zr
= B𝜔r (t − t6) + ir (t6). (17)
Mode 8 (t7 < t < t8): At t7, the voltage of auxiliary
winding of SR2 is reduced to less than the threshold volt-
age. Hence, SR2 is turned off while its anti-parallel diode d3 is
still conducting. The preceding equations remain valid for this
period, since the substitution of SR2 with its anti-parallel diode
applies no changes in equations. The switch Q2 is turned off
at t8.
The capacitor C2 keeps the voltage across Q2 almost con-
stant at zero and therefore Q2 turn-off is performed at the ZVS
NOURIEH ET AL. 5
conditions.
Tx = T7 + T8 =
𝜙3
𝜔r
, (18)
ix = i7 + i8. (19)
Mode 9 (t8 < t < t9): By turning Q2 off at t8, the flow of the
remaining current in Lr continues through C1 and C2 resulting
in vM increasing until its value reaches VS at t9.
vr (t )
Vs
= Vs
[(
−Ix
√
𝛼
)
sin(𝜔r
√
𝛼(t − tx))
+ B cos(𝜔r
√
𝛼(t − tx)) − B
]
(20)
ir (t )
Vs∕Zr
=
[
B√
𝛼
sin(𝜔r
√
𝛼(t − tx)) + Ix cos(𝜔r
√
𝛼(t − tx))
]
(21)
T9 =
1√
𝛼𝜔r
cos−1
[
I9Ix (𝛼 + B)(1 + B)
B2 + aI 25
]
(22)
ir (t )
Vs∕Zr
= 𝜔r (t − t9) + ir (t9), (23)
t10 − t9 =
ir (t9)
𝜔r
. (24)
Mode 10 (t9 < t < t10): By reaching vM toVS at t9, the diode
d1 is turned on at ZVS and ir flows through it until it becomes
zero at t10. Then, d1 and Qr are turned off at ZCS conditions.
At any desired time during this mode, the gate signal of Q1 is
set to turn it on at ZVS condition in the next cycle. It should
be mentioned here that no additional mode will be added by C3
and C4.
3 SELF-DRIVEN SYNCHRONOUS
RECTIFIER
Considering the literature of driving synchronous rectifiers,
there are two methods for driving SR MOSFETs: external and
internal gate drivers. This paper uses the latter in the SR stage
of the proposed converter. As shown in Figure 1, SR1 and
SR2 function as a synchronous rectifier and together R1, R2,
C3, C4 as well as Zener diodes protect the SDSR circuit; the
transformer auxiliary windings generate the gate signals pro-
tected by the back-to-back Zener diodes; also series of resis-
tors control the driving current (Figure 4). The simplicity of this
self-driven circuit is one of the advantages of the proposed con-
verter. Enhanced driving circuits may also be employed for fur-
ther improvement of the system performance at the cost of the
circuit complexity [10, 11]. Figure 5 shows the schematic model
of the constructed transformer with five layers of winding. Con-
FIGURE 4 Output side of proposed converter with SDSR
FIGURE 5 Transformer construction model
sidering the number of winding layers, core size, diameter of
wire and the distance between each turn of wire, in this circuit
the transformer leakage inductance is used as a whole resonant
inductance (i.e. Llk = Lr). Thus, the transformer leakage induc-
tance is not problematic. However, its value effects on the reso-
nant tank characteristic impedance Zr which controls the output
power. Furthermore, there is a reflected inductance of 2.7 uH on
the secondary side which is called Lss in Figure 1. This reflected
inductance is large enough for the synchronous rectifier to work
well. To increase the converter power handling capability, the
resonant inductor should be small enough and then the trans-
former leakage inductance should be kept as small as possible.
3.1 Geometry construction of transformer
As shown in Figure 5, the primary winding (NP) is the first layer,
then the secondary windings (NS1 and NS2) are wound as close
as possible toNP. The windings ofNS1 andNS2 should be sym-
metric with respect to the transformer center line. Then, the
auxiliary windings are wound symmetrically; NA1 is wound on
NS1 where NA2 is on NS2. Appropriate range of the auxiliary
turn number can be found in Equation (25).
6 NOURIEH ET AL.
where Vth,max and VGS,max are the maximum threshold-
voltage and gate-source voltage of the SR MOSFET, respec-
tively. Lower values forNA/NS results in improper turn on, and
higher values results in overcurrent and heating up of the gate
resistors.
Vth,max
VO
<
NA
NS
<
VGS ,max
VO
(25)
√
1 −
(
Lss
Lm
)2
= k (26)
Moreover, as it is explained in Appendix, the value of n is 10
(B = 0.33). Thus, NA should be a number between 0.8 and 4,
which is considered as 2 (notice thatNS = 1).
Among all types of cores, ferrite cores are generally used for
switching power supplies. Ferrites can work during operation
at higher flux densities and frequencies. Among different fer-
rite cores, the PQ cores with high flux density and permeabil-
ity are applicable for power supplies. Concluding all reasons
given, the PQ 40/40 core is selected. To improve the perfor-
mance and to decrease the size of circuit together, three trans-
formers are merged into one in this paper. Also, to have a
lower leakage inductance, all gaps are avoided between cores.
Another factor which is very important to take into account is
transformer coupling. Considering Equation (26), by using PQ
40/40, an excellent coupling of 0.99 will be reached for trans-
former (Lm = 19 uH attained in PSPICE).
4 EXPERIMENTAL RESULTS
A prototype of the proposed converter with SDSR was
made in laboratory with specifications such as: input volt-
age Vs = 150 V, output voltage Vo = 5 V, output current
Io = 20 A, switching frequency fs-full = 220 kHz for full-
load waveforms, and fs-light = 330 kHz for light-load wave-
forms. Furthermore, the components used in this converter
are: Q1 = Q2 = Qr = IRF640, SR1 = SR2 = IRF1404, and
Cr = 23 nF (SMD/600 V). The gate signal for the switches in
the primary side has been produced by the external gate drivers.
For the resonant inductance, the leakage inductance of trans-
former is used as Llk = 25 μH. To measure currents of Q1¸ Q2,
and Lr, two resistors of 0.5 and 0.33 Ω are used for full-load
and light-load modes, respectively. Considering fr = 202 kHz
(selected close to fs = 220 kHz), C1 = C2 (symmetrical design),
overdesign= 1.2, α= 6 (explained in Appendix), and the Equa-
tions Equations (1), (2), and (28), the values of Cr, Lr, C1, and
C2 are attained, as presented in Table 1. It should be mentioned
that fs and Pout for full-load are equal to 220 kHz and 100 W,
while they are 330 kHz and 20 W for light-load, respectively. To
wind the transformer, a wire with diameter of 0.55 mm is used
for the primary side as well as two parallel wires with diameters
of 0.55 mm for the secondary side.
To have a reliable self-driven method, a wire with diameter of
0.25 mm is used to transfer both SRs gate signals. In addition,
TABLE 1 Parameters and components of the circuit
Symbol Full-Load—Light-load
Vs 150 V
Vo 5 V
Pout 100–20 W
fs 220–330 kHz
Cr 23 nF
Lr 25 μH
C1 1 nF
C2 1 nF
R1 0.5 Ω
R2 0.5 Ω
fr 202 kHz
V
GS1
: 10V/div
V
DS2
: 50V/div
I1: 2A/div
V
r
: 50V/div
Time[1us]
Time[1us]
Time[1us]
Time[1us]
ZVS OFF ZVS ON
FIGURE 6 Practical waveforms for Q1 and resonant voltage in full load
mode (Pout = 100 W, fs = 220 kHz, 1 us/div, Period = 4.54 us)
Figures 6 and 7 show practical waveforms for primary side of
transformer in full-load case, where both “ZVS turn-on” and
“ZVS turn-off” are obtained for Q1 and Q2. In addition, it is
demonstrated that currents of Q1 and Q2 are negative for a
few tenths of microseconds, when the primary side switches are
turned on and off. It should be noted that the horizontal axes in
all figures from Figures 6–11 represents time with time division
mentioned below each figure, while the vertical axe is defined
above each figure.
The behavior of vr and ir is also shown in Figures 6 and 7,
where vr rises until the moment ir becomes negative. At this
time, vr starts decreasing gradually to zero, when Qr is turned
on for transferring magnetic energy stored in Lr to the output,
NOURIEH ET AL. 7
V
GS2
: 10V/div
V
DS2
: 50V/div
I
2
: 2A/div
I
r
: 2A/div
Time[1us]
Time[1us]
Time[1us]
Time[1us]
ZVS OFFZVS ON
FIGURE 7 Practical waveforms for Q2 and resonant current in full load
mode (Pout = 100 W, fs = 220 kHz, 1 us/div, Period = 4.54 us)
V
GS(SR)
: 10V/div
A/div
V
DS(SR1)
: 10V/div
V
DS(SR2)
: 10V/div
Time[1us]
Time[1us]
Time[1us]
Overlap
FIGURE 8 Practical waveforms for secondary side in full load mode
(Pout = 100 W, fs = 220 kHz, 1 us/div, Period = 4.54 us)
V
GS1
: 10V/div
V
DS2
: 50V/div
I
1
: 1A/div
V
r
: 50V/div
Time[1us]
Time[1us]
Time[1us]
Time[1us]
ZVS ONZVS OFF
FIGURE 9 Practical waveforms for Q1 and resonant voltage in light load
mode (Pout = 20 W, fs = 330 kHz, 1 us/div, Period = 3.03 us)
V
GS2
: 10V/div
V
DS2
: 50V/div
I
2
: 1A/div
I
r
: 1A/div
Time[1us]
Time[1us]
Time[1us]
Time[1us]
ZVS OFFZVS ON
FIGURE 10 Practical waveforms for Q2 and resonant current in light
load mode (Pout = 20 W, fs = 330 kHz, 1 us/div, Period = 3.03 us)
8 NOURIEH ET AL.
V
GS(SR1)
: 10V/div
A/div
V
DS(SR1)
: 10V/div
V
GS(SR2)
: 10V/div
A/div
V
DS(SR1)
: 10V/div
Time[1us]
Time[1us]
Time[1us]
Time[1us]
Overlap
FIGURE 11 Practical waveforms for secondary side in light load mode
(Pout = 20 W, fs = 330 kHz, 1 us/div, Period = 3.03 us)
resulting in the linear reduction of ir. In Figure 8, experimental
waveforms of secondary side are illustrated, where both gate
signals generated from a transformer with self-driven circuit
and two drain-source voltages of SRs with indicated overlapping
periods are highlighted. Figures 9 and 10 show practical wave-
forms of the prototype for Q1, Q2, vr, and ir in the light-load
case. Similar to full-load approach, “ZVS turn-on” and “ZVS
turn-off” are attained for both Q1 and Q2. Compared to full
load case, the period of Qr conducting is very short; in other
words, the linear interval is not long compared to others.
The gate signals produced by the transformers are very
appropriate for running both SRs correctly as shown in Fig-
ure 11. In Figure 12, the output voltages for both modes are
shown where the Rout is 0.25 and 1.175Ω for full-load and light-
load, respectively.
As shown in Figure 13, reducing fn (fn = fs/fr) increases the
output power. Thus, by selecting two close values for resonant
and switching frequencies, that is, fr and fs, the output power will
rise. Figure 14 shows the impact of output power on efficiency
of the proposed converter.
A comparison between different converters is also shown in
Figure 14. It should be mentioned that the winding capacitance
of the proposed converter in secondary side is low enough to be
neglected. Furthermore, in the primary side, the winding capac-
itance is not problematic, since the resonant capacitor is 23 nF;
thus, the winding capacitance which is about pF, is absorbed
by Cr. As illustrated in Figure 14, for a range of output powers
(c)
(a)
(b)
Vout: 5V/div
Vout: 5V/div
Time: 2.5us/div
0
0
5
1 2
Time: 1us/div
3 4 -2 -1 -4 -3
-5 -2.5 -7.5 -10 2.5 5 7.5 10
Vout: 5V/div
Time: 100ns/div
5
5
0
-400 -300 -200 -100 100 200 300 400
FIGURE 12 Output voltage. (a) Output voltage of full-load mode
(Pout = 100 W, fs = 220 kHz, 2.5 us/div, 5 V/div), (b) Output voltage of
light-load mode (Pout = 20 W, fs = 330 kHz, 1 us/div, 5 V/div), (c) Output
voltage ripple of full-load (Pout = 100 W, fs = 220 kHz, 100 ns/div, 5 V/div)
Output power [Watt]
FIGURE 13 Ratio of switching frequency to resonant frequency for
different output powers
Output power [Watt]
FIGURE 14 Efficiency versus output power
NOURIEH ET AL. 9
FIGURE 15 Converter prototype
between light-load and full-load cases, the proposed converter
including diode-connected MOSFET in the active tank with
SDSR has a higher efficiency than the one working with diode in
the resonant tank. The efficiency has a slight rise from 91.9% to
94.95% for diode-connected MOSFET with SDSR and a grad-
ual rise from 91.2% to 94.35% for the converter with diode in
resonant tank and SDSR in rectification section, which shows a
slight better performance of this circuit. Furthermore, the pro-
posed structure of the converter with diode in active tank and
rectifier has the efficiency gradually raised from 72% to 89% for
different output powers [30, 31]. This comparison can show the
slightly better efficiency of the proposed converter with diode-
connected MOSFET and SDSR. Comparing all experimental
and theoretical waveforms, the correctness of theoretical analy-
sis is verified. Finally, Figure 15 shows the manufactured labo-
ratory prototype. Regarding the size of the converter, the main
PCB board size is 15 cm × 10 cm where the bulky part of con-
structed converter is the transformer core (PQ 40/40).
Considering the problems that can arise from mismatch in
converter operation, we will further discuss it in detail in the
subsequent paragraphs. Mismatch in transformer design such as
turn-ratio can affect the performance of the converter. Firstly,
change in the transformer turn-ratio can affect power conver-
sion, voltage, and current as they are a function of the ratio.
However, in transformer design, the turn-ratio can be kept rel-
atively constant since a small mismatch in transformer design
could hardly change the number of turns in the transformer
primary and secondary sides. Secondly, mismatch in turn-ratio,
geometry of construction, or distance between coil windings of
a transformer may change the leakage inductance of the trans-
former, reflected on the primary and secondary sides, which
may further affect the active resonant frequency and voltage
level. However, we would not expect that such changes are
significant due to our careful design, and if it is necessary,
small change in the leakage inductance can be compensated
by adding a small inductor in series or parallel depending on
if the leakage inductance becomes smaller or larger due to the
mismatch.
Finally, mismatch in transformer design may affect its resis-
tance and thus the converter efficiency. This is less significant
though, as in the design of the transformer we have very few
TABLE 2 Comparison of the proposed converter and prior art
References Features [7] [31] [27]
Proposed
converter
Input voltage 12 V 390 V 120 V 150 V
Output voltage/Current 5 V/2 A 12 V/25 A 80 V/8 A 5 V/20 A
Maximum efficiency 79.50% 92.50% 93.00% 94.95%
Switching frequency 40 kHz 110 kHz 180 kHz 220 kHz
Resonant frequency 40 kHz 56 kHz 167 kHz 202 kHz
Self-driven circuit No No No Yes
Zero-voltage switching No Yes Yes Yes
turns of windings to achieve the desired inductance which leads
to very small negligible resistance in the transformer. Thus,
any possible change in transformer resistance due to mismatch
would unlikely increase the transformer resistance and decrease
the converter efficiency significantly.
Table 2 compares the performance of the proposed converter
with prior researches [7, 27, 31] in terms of power efficiency,
switching and resonant frequencies, self-drive, and ZVS meth-
ods. The proposed converter provides better efficiency than the
others as seen in Table 2. Furthermore, the significant higher
switching and resonant frequencies are applied in the proposed
converter, which contribute to the high efficiency. Additionally,
comparisons are made in terms of self-driven gate driver used
for SRs which leads to reduced gate driver losses and whole con-
verter size by omitting the external gate drivers, as well as the
ZVS condition which provides advantages such as lower switch-
ing and capacitance losses.
5 POWER LOSS ANALYSIS
The proposed converter mentioned here benefits from low
switching, conducting and thermal losses due to ZVS condition
which removes not only the switch voltage–current overlap, but
also the losses produced by the MOSFET output capacitance
(Coss) and reverse recovery of PN junctions. Hence, the main
power loss in the proposed circuit is created due to the over-
lap occurred in two drain-source voltages of SRs in the output
section. Considering the efficiency and input power of the con-
verter, the total power dissipation can be calculated as 5.05 Watt
in full-load and 1.65 Watt in light-load condition.
With regards to voltage gain in a constant state, the voltage
gain can be found by using energy balance in one switching
cycle. In Equations (27) and (28), input and output energy as
well as voltage gain are shown as εin, εout and A, respectively.
Considering that εin should be equal to εout, the final equation is
found for A which will further help to find the theoretical value
of different elements in circuit.
⎧⎪⎨⎪⎩
𝜀out =
1
R ∫Ts V
2
o dt ≅
V 2o Ts
R
𝜀in = 2(1 − B)CrV
2
s
, (27)
10 NOURIEH ET AL.
⎧⎪⎨⎪⎩
𝜀in = 𝜀out ,
A = −nRCr fs +
√
n2R2Cr
2 fs
2 + RCr fs
. (28)
6 CONCLUSION
A new isolated resonant converter with ZVS and SDSR is pre-
sented for low-voltage and high-current applications. The active
resonant tank is composed of a transformer leakage inductance,
a capacitor, and a diode-connected MOSFET in the primary
side which provides ZVS conditions for all switches. A simple
SDSR with a center-tapped transformer is employed at the sec-
ondary side to improve converter performance. The converter
itself produces the required gate signals to run MOSFETs in
a synchronous rectifier. Due to the use of transformer leakage
inductance in the primary and secondary side as the resonant
and output inductors, respectively, there is no need to add any
further external inductor, resulting in a major size reduction of
the circuit. Experimental results show that the power efficien-
cies of the converter including SDSR for the light load and the
full load are 91.9% and 94.95% at output power Pout = 20 W
and Pout = 100 W, respectively.
FUNDING
None.
ORCID
NajmehossadatNourieh https://orcid.org/0000-0003-0439-
6076
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NOURIEH ET AL. 11
How to cite this article: Nourieh, N., Sun, Y.,
Simpson, O.: A novel resonant ZVS power converter
with self-driven synchronous rectifier for low-voltage
high-current applications. IET Power Electron. 1–12
(2021). https://doi.org/10.1049/pel2.12116
APPENDICES
ZVS Analyses: The conditions needed to provide ZVS opera-
tion are studied in [29] and presented here. ZVS operation for
bothQ1 andQ2 are considered. At the end of mode 3, if ir is still
positive, the anti-parallel diode of Q2 will be turned on at the
next interval and consequently ZVS turn-on is achieved for Q2.
It can be shown this constraint leads to the inequality of Equa-
tion (A1) where Bmax is a maximum for normalized voltage gain
B = nA. Considering thatVM should decrease fromVS to zero,
energy in Lr would remain enough at t2. So, ir(t3) is set larger
than zero ir(t3) > 0 and then to have root for this inequality,
∆ should be greater than zero ∆ ≥ 0. Solving this inequality,
Bmax is found. Having Bmax and solving ir(t3) > 0, the roots are
found as it is shown in Figure 4. For different values of α, φ1u is
always between 1 and −1. As a result, the inequality of φ1 < φ1u
is reached for the whole range of B < Bmax in Equation (A1).
Considering Figure A1(a), it is shown that for some values of
B, φ1k > 1. Thus, φ1k should be limited to φ1k < 1. Solving
this inequality, a new value for B, named Bk, is achieved (Fig-
ure A1(b)). In this figure, Bk is always less than Bmax. So two
conditions for Q2 ZVS turn-on are reached in Equations (A2)
and (A3).
B ≤ Bmax, Bmax = 1 − 1√
𝛼
(A1)
𝜙1U = cos
−1
[
1
𝛼(1 − B)
−
√
1 −
1
𝛼(1 − B)2
]
, (A2)
𝜙1K = cos
−1
[
1
𝛼(1 − B)
+
√
1 −
1
𝛼(1 − B)2
]
At mode 9, the voltage VM can reach Vs if Equation (A4)
is satisfied (ZVS turn-on conditions for Q1). The constraint
of Equation (A4) results in φ3 has an upper limit as φ3u which is
given by Equation (A5). Solving the inequality of φ3u > 0, two
roots are found, named φ1f and φ2f (Figure A1(c)). Regarding
Figure A1(c) for whole range of α, φ2f is greater than 1 but for
some cases φ1f ≤ −1. The limitation of 1 > φ1f≥ −1 should be
considered. Solving the inequality φ1f≥ −1 by curve fitting in
MATLAB, a new value for B is found, named Bd. Figure A1(d)
shows the graphs plotted for Bmax, Bd, and Bk. As shown in this
0 0.05 0.15 0.250.20.1 0.3 0.35 0.45 0.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1K
1u
0.4
B 0 0.02 0.04 0.06 0.10.08 0.12 0.14 0.16 0.18 0.2
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
2f
1f
B
(c)(b)(a)
(d) (e)
0 10 20 30 40 50 60 70 80 90 100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
B
max
B
k
B
1 2 3 4 5 6 7 8 9 10
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
B
k
B
d
B
max
B
0 0.0 0.1 0.15 0.2 0.2 0.3 0.3 0.4 0.45
0.5
1
1.5
2
2.5
3
1u
1f
B
FIGURE A1 Graphs plotted in MATLAB: (a) φ1U and φ1K versus φ, (b) B versus α, (c) φ2f and φ1f versus φ, (d) Bd, Bmax, Bk versus α, (e) φ1f and φ1u versus B
12 NOURIEH ET AL.
figure, Bk is always less than Bmax. Therefore, the inequality of
B < (0.5,Bmax,Bd) should be considered and then the result of
this unity is φ1f < φ1u (Figure A1(e)). As shown in Figure A1(e)
for some values of α, φ1f is less than φ1u. To solve it, curve
fitting method is used and it results in Bf in Equation (A6). Con-
cluding all these conditions for B, the best values for B and α are
0.33 and 6 (a number between 5.5 and 6.5), respectively. Thus,
the proper value for n is 10.{{
B < Bk
𝜙1 < 𝜙 1u
,
{
B > Bk
𝜙1k < 𝜙1 < 𝜙1u
(A3)
||ir (t7) + ir (t8)|| ≥√1 + 2B𝛼 → 𝜙3 ≤ 𝜙3U (A4)
𝜙3U =
√
(2B − 𝛾)2 − B2
B2
−
√
2B + 1
𝛼B2
> 0 (A5)
⎧⎪⎨⎪⎩
Bd =
0.5a + 0.231
a + 1.263
B f =
a + 1
2a + 0.7574
(A6)