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        Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

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        904848.pdf (PDF, 1Mb)
        Author
        Zhai, Xiaojun
        Bensaali, Faycal
        Ramalingam, Soodamani
        Attention
        2299/11089
        Abstract
        Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images respectively, both with a resolution of "640×480" , have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms whilst achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.
        Publication date
        2013-03
        Published in
        IET Circuits, Devices & Systems
        Published version
        https://doi.org/10.1049/iet-cds.2012.0064
        Other links
        http://hdl.handle.net/2299/11089
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