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dc.contributor.authorZhai, Xiaojun
dc.contributor.authorBensaali, Faycal
dc.contributor.authorRamalingam, Soodamani
dc.date.accessioned2013-07-16T10:17:29Z
dc.date.available2013-07-16T10:17:29Z
dc.date.issued2013-03
dc.identifier.citationZhai , X , Bensaali , F & Ramalingam , S 2013 , ' Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation ' , IET Circuits, Devices & Systems , vol. 7 , no. 2 , pp. 93-103 . https://doi.org/10.1049/iet-cds.2012.0064
dc.identifier.issn1751-8598
dc.identifier.otherPURE: 1047057
dc.identifier.otherPURE UUID: d6d4804e-6a8e-4539-84b5-b1d38a437109
dc.identifier.otherScopus: 84880655526
dc.identifier.urihttp://hdl.handle.net/2299/11089
dc.description.abstractNumber plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images respectively, both with a resolution of "640×480" , have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms whilst achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.en
dc.language.isoeng
dc.relation.ispartofIET Circuits, Devices & Systems
dc.rightsOpen
dc.titleImproved number plate localisation algorithm and its efficient field programmable gate arrays implementationen
dc.contributor.institutionSchool of Engineering and Technology
dc.contributor.institutionScience & Technology Research Institute
dc.contributor.institutionDigital Media Processing and Biometrics
dc.contributor.institutionCentre for Engineering Research
dc.contributor.institutionSmart Electronics Devices and Networks
dc.description.statusPeer reviewed
dc.relation.schoolSchool of Engineering and Technology
dc.description.versiontypeFinal Accepted Version
dcterms.dateAccepted2013-03
rioxxterms.versionAM
rioxxterms.versionofrecordhttps://doi.org/10.1049/iet-cds.2012.0064
rioxxterms.typeJournal Article/Review
herts.preservation.rarelyaccessedtrue
herts.rights.accesstypeOpen


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