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        Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture

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        901719.pdf (PDF, 448Kb)
        Author
        Egan, C.
        Steven, F.L.
        Steven, G.B.
        Attention
        2299/1582
        Abstract
        While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the context of a high-performance superscalar architecture that uses aggressive compile-time instruction scheduling.
        Publication date
        1997
        Published in
        In: EUROMICRO 97 'New Frontiers of Information Technology' short communications, Procs of the 23rd Conf
        Other links
        http://hdl.handle.net/2299/1582
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