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Browsing University of Hertfordshire by Author "Gray, S.M."
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HARP: A Parallel Pipelined RISC Processor
Steven, G.B.; Gray, S.M.; Adams, R.G. (1989)HARP (the Hatfield RISC processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a RISC processor capable of a sustained instruction ... -
HARP: a statically scheduled multiple-instruction-issue architecture and its compiler
Adams, R.G.; Gray, S.M.; Steven, G.B. (University of Hertfordshire, 1994)This paper presents the results of an investigation into the performance of a new statically scheduled multiple-instruction-issue architecture and its compiler. HARP is a Long Instruction Word Architecture developed in ... -
Static instruction scheduling for the HARP multiple-instruction-issue architecture
Gray, S.M.; Adams, R.G.; Green, G.J.; Steven, G.B. (University of Hertfordshire, 1992)HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, ... -
Static Instruction Scheduling for the HARP Multiple-Instruction-Issue Architecture
Gray, S.M.; Adams, R.G.; Green, G.J.; Steven, G.B. (1993)HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, ... -
Using conditional execution to exploit instruction level concurrency
Gray, S.M.; Adams, R.G. (University of Hertfordshire, 1994)Multiple-instruction-issue processors seek to improve performance over scalar RISC processors by providing multiple pipelined functional units in order to fetch, decode and execute several instructions per cycle. The process ... -
Using Conditional Execution to Exploit Instruction Level Concurrency
Adams, R.G.; Gray, S.M. (1995)