Search
Now showing items 1-2 of 2
A superscalar architecture to exploit instruction level parallelism
(1997-03-17)
If a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent ...
An introduction to the Hatfield superscalar architecture
(University of Hertfordshire, 1996)
If a high-performance superscalar processor is to realise its full potential, the complier must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent ...