| dc.contributor.author | Elston, C.J. | |
| dc.date.accessioned | 2010-09-28T13:44:04Z | |
| dc.date.available | 2010-09-28T13:44:04Z | |
| dc.date.issued | 1994 | |
| dc.identifier.citation | Elston , C J 1994 , Potential for asynchronous microprocessor design . UH Computer Science Technical Report , vol. 182 , University of Hertfordshire . | |
| dc.identifier.other | dspace: 2299/4851 | |
| dc.identifier.uri | http://hdl.handle.net/2299/4851 | |
| dc.description.abstract | Asynchronous (non-globally clocked) design and realisation of processors is undergoing a resurgence of interest. The difficulties of producing complex, high performance synchronous (globally clocked) processors are becoming severe and these problems will only be compounded by technological advancement. Asynchronous design has its own associated difficulties in producing functionally correct, high performance processors but there is the potential to increase performance and simplify design. This report outlines a number of promising approaches to asynchronous design giving the advantages and disadvantages of each in the context of present and future environments. | en |
| dc.format.extent | 3691448 | |
| dc.language.iso | eng | |
| dc.publisher | University of Hertfordshire | |
| dc.relation.ispartofseries | UH Computer Science Technical Report | |
| dc.subject | microprocessor design | |
| dc.subject | asynchronous systems | |
| dc.subject | delay-insensitive circuits | |
| dc.subject | apeed-independent circuits | |
| dc.subject | micropipelines | |
| dc.title | Potential for asynchronous microprocessor design | en |
| dc.contributor.institution | School of Computer Science | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
