| dc.contributor.author | Zhu, X. | |
| dc.contributor.author | Sun, Y. | |
| dc.contributor.author | Moritz, J. | |
| dc.date.accessioned | 2012-01-04T17:01:09Z | |
| dc.date.available | 2012-01-04T17:01:09Z | |
| dc.date.issued | 2007 | |
| dc.identifier.citation | Zhu , X , Sun , Y & Moritz , J 2007 , A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter . in Procs 50th IEEE Int Midwest Symposium on Circuits & Systems . vol. 2007 , Institute of Electrical and Electronics Engineers (IEEE) , pp. 167-170 . https://doi.org/10.1109/MWSCAS.2007.4488563 | |
| dc.identifier.isbn | 978-1-4244-1175-7 | |
| dc.identifier.other | dspace: 2299/4746 | |
| dc.identifier.uri | http://hdl.handle.net/2299/7599 | |
| dc.description | “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” | |
| dc.description.abstract | Read/write channels for hard disk drives (HDD) require high-frequency continuous time filters (CTF). A 650 MHz current-mode seventh-order 0.05deg equiripple linear phase low-pass filter for computer hard disk read/write channels with data rates up to 1 Gbit/s is presented in this paper. It is implemented in CMOS using a leap-frog multiple loop feedback structure. The operational transconductance amplifier (OTA) used is based on a differential pair and uses source degeneration to achieve linearization and tuning. Simulated using a standard 0.18 mum CMOS process, the dynamic range at 1% THD of the filter is 48 dB, cut-off frequency can be tuned from 590 MHz to 690 MHz, group delay ripple is about 5%, and power consumption is 370 mW from supply voltage of 2.5 V. | en |
| dc.format.extent | 474089 | |
| dc.language.iso | eng | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | |
| dc.relation.ispartof | Procs 50th IEEE Int Midwest Symposium on Circuits & Systems | |
| dc.title | A CMOS 650 MHz seventh-order current-mode 0.05° equiripple linear phase filter | en |
| dc.contributor.institution | School of Engineering and Technology | |
| dc.contributor.institution | Science & Technology Research Institute | |
| rioxxterms.versionofrecord | 10.1109/MWSCAS.2007.4488563 | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
