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Hades - towards the design of an asynchronous superscalar processor
Elston, C.J.; Christianson, B.; Findlay, P.; Steven, G.B. (University of Hertfordshire, 1995)Hades is a processor architecture aimed at single and multiple-instruction-issue asynchronous implementations. This paper uses a baseline version of Hades to illustrate some of the difficulties encountered in asynchronous ... -
Potential for asynchronous microprocessor design
Elston, C.J. (University of Hertfordshire, 1994)Asynchronous (non-globally clocked) design and realisation of processors is undergoing a resurgence of interest. The difficulties of producing complex, high performance synchronous (globally clocked) processors are becoming ... -
Register bypassing in an asynchronous superscalar processor
Davies, S.J.; Elston, C.J.; Findlay, P. (University of Hertfordshire, 1999)Register bypassing, universally provided in synchronous processors, is more difficult to implement in an asynchronous design. Asynchronous bypassing requires synchronization between the forwarding and receiving units, with ...