Browsing by Author "Galivanche, Rajesh"

Now showing items 1-2 of 2

    • Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 

      Omana, Martin; Rossi, Daniele; Beniamino, Edda; Metra, Cecilia; Tirumurti, Chandra; Galivanche, Rajesh (2016-08-31)
      During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. ...

    • Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 

      Omana, Martin; Rossi, Daniele; Fuzzi, Filippo; Metra, Cecilia; Tirumurti, Chandra; Galivanche, Rajesh (2017-01-31)
      The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of ...