Browsing by Author "Omana, Martin"

Now showing items 1-6 of 6

    • Impact of Aging Phenomena on Latches’ Robustness 

      Omana, Martin; Rossi, Daniele; Edara, TusharaSandeep; Metra, Cecilia (2016-03-08)
      In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of both standard and robust latches. Particularly, we consider bias temperature instability (BTI) affecting both nMOS (positive ...

    • Impact of Bias Temperature Instability on Soft Error Susceptibility 

      Rossi, Daniele; Omana, Martin; Metra, Cecilia; Paccagnella, Alessandro (2015-04-30)
      In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors ...

    • Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 

      Omana, Martin; Rossi, Daniele; Beniamino, Edda; Metra, Cecilia; Tirumurti, Chandra; Galivanche, Rajesh (2016-08-31)
      During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. ...

    • Low-Cost On-Chip Clock Jitter Measurement Scheme 

      Omana, Martin; Rossi, Daniele; Giaffreda, Daniele; Metra, Cecilia; Mak, TM; Raman, Asifur; Tam, Simon (2015-03-01)
      In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high ...

    • Modeling and Detection of Hotspot in Shaded Photovoltaic Cells 

      Rossi, Daniele; Omana, Martin; Giaffreda, Daniele; Metra, Cecilia (2015-06-01)
      In this paper, we address the problem of modeling the thermal behavior of photovoltaic (PV) cells undergoing a hotspot condition. In case of shading, PV cells may experience a dramatic temperature increase, with consequent ...

    • Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 

      Omana, Martin; Rossi, Daniele; Fuzzi, Filippo; Metra, Cecilia; Tirumurti, Chandra; Galivanche, Rajesh (2017-01-31)
      The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of ...