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dc.contributor.authorZhai, Xiaojun
dc.contributor.authorBensaali, Faycal
dc.contributor.authorSotudeh, Reza
dc.date.accessioned2013-07-16T09:32:29Z
dc.date.available2013-07-16T09:32:29Z
dc.date.issued2013-01
dc.identifier.citationZhai , X , Bensaali , F & Sotudeh , R 2013 , ' Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems ' , Journal of Electronic Imaging , vol. 22 , no. 1 , 013009 . https://doi.org/10.1117/1.JEI.22.1.013009
dc.identifier.issn1560-229x
dc.identifier.otherPURE: 1400469
dc.identifier.otherPURE UUID: 4774295c-5df5-4576-9cc0-cffc0170016c
dc.identifier.otherScopus: 84879942972
dc.identifier.urihttp://hdl.handle.net/2299/11086
dc.descriptionCopyright 2013 Society of Photo-Optical Instrumentation Engineers. One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited
dc.description.abstractNumber Plate (NP) binarisation and adjustment are very important pre-processing stages in Automatic Number Plate Recognition (ANPR) systems and are used to link the Number Plate Localisation (NPL) and Character segmentation (CS) stages. Successfully linking these two stages will improve the performance of the entire ANPR system. This paper presents two optimised low complexity NP binarisation and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07-0.17ms.en
dc.language.isoeng
dc.relation.ispartofJournal of Electronic Imaging
dc.titleField programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systemsen
dc.contributor.institutionSchool of Engineering and Technology
dc.contributor.institutionScience & Technology Research Institute
dc.contributor.institutionDigital Media Processing and Biometrics
dc.contributor.institutionCentre for Engineering Research
dc.contributor.institutionSmart Electronics Devices and Networks
dc.description.statusPeer reviewed
rioxxterms.versionAM
rioxxterms.versionofrecordhttps://doi.org/10.1117/1.JEI.22.1.013009
rioxxterms.typeJournal Article/Review
herts.preservation.rarelyaccessedtrue


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