dc.contributor.author | Zhai, Xiaojun | |
dc.contributor.author | Bensaali, Faycal | |
dc.contributor.author | Sotudeh, Reza | |
dc.date.accessioned | 2013-07-16T09:32:29Z | |
dc.date.available | 2013-07-16T09:32:29Z | |
dc.date.issued | 2013-01 | |
dc.identifier.citation | Zhai , X , Bensaali , F & Sotudeh , R 2013 , ' Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems ' , Journal of Electronic Imaging , vol. 22 , no. 1 , 013009 . https://doi.org/10.1117/1.JEI.22.1.013009 | |
dc.identifier.issn | 1560-229x | |
dc.identifier.other | PURE: 1400469 | |
dc.identifier.other | PURE UUID: 4774295c-5df5-4576-9cc0-cffc0170016c | |
dc.identifier.other | Scopus: 84879942972 | |
dc.identifier.uri | http://hdl.handle.net/2299/11086 | |
dc.description | Copyright 2013 Society of Photo-Optical Instrumentation Engineers. One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited | |
dc.description.abstract | Number Plate (NP) binarisation and adjustment are very important pre-processing stages in Automatic Number Plate Recognition (ANPR) systems and are used to link the Number Plate Localisation (NPL) and Character segmentation (CS) stages. Successfully linking these two stages will improve the performance of the entire ANPR system. This paper presents two optimised low complexity NP binarisation and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07-0.17ms. | en |
dc.language.iso | eng | |
dc.relation.ispartof | Journal of Electronic Imaging | |
dc.rights | Open | |
dc.title | Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems | en |
dc.contributor.institution | School of Engineering and Technology | |
dc.contributor.institution | Science & Technology Research Institute | |
dc.contributor.institution | Digital Media Processing and Biometrics | |
dc.contributor.institution | Centre for Engineering Research | |
dc.contributor.institution | Smart Electronics Devices and Networks | |
dc.description.status | Peer reviewed | |
dc.description.versiontype | Final Accepted Version | |
dcterms.dateAccepted | 2013-01 | |
rioxxterms.version | AM | |
rioxxterms.versionofrecord | https://doi.org/10.1117/1.JEI.22.1.013009 | |
rioxxterms.type | Journal Article/Review | |
herts.preservation.rarelyaccessed | true | |
herts.rights.accesstype | Open | |