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dc.contributor.authorSteven, G.B.
dc.contributor.authorChristianson, B.
dc.contributor.authorCollins, R.
dc.contributor.authorSteven, F.L.
dc.contributor.authorPotter, R.
dc.identifier.citationSteven , G B , Christianson , B , Collins , R , Steven , F L & Potter , R 1997 , ' A superscalar architecture to exploit instruction level parallelism ' , Microprocessors and Microsystems , vol. 20 , no. 7 , pp. 391-400 .
dc.identifier.otherPURE: 8160722
dc.identifier.otherPURE UUID: 861a8c97-8215-43d7-8fe8-fa9fd5c0cf3b
dc.identifier.otherScopus: 0042045541
dc.description.abstractIf a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent and which therefore can be issued and executed in parallel at run time. This paper provides an overview of the Hatfield Superscalar Architecture (HSA), a multipleinstruction-issue architecture developed at the University of Hertfordshire to support the development of high-performance instruction schedulers. The long-term objective of the HSA project is to develop the scheduling technology to realise an order of magnitude performance improvement over traditional RISC designs. The paper also presents results from the first HSA instruction scheduler that currently achieves a speedup of over three compared to a classic RISC processor.en
dc.relation.ispartofMicroprocessors and Microsystems
dc.titleA superscalar architecture to exploit instruction level parallelismen
dc.contributor.institutionCentre for Computer Science and Informatics Research
dc.description.statusPeer reviewed
rioxxterms.typeJournal Article/Review

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