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dc.contributor.authorAdams, R.G.
dc.contributor.authorSteven, G.B.
dc.date.accessioned2008-02-05T12:23:18Z
dc.date.available2008-02-05T12:23:18Z
dc.date.issued1991
dc.identifier.citationAdams , R G & Steven , G B 1991 , ' A Parallel Pipelined Processor with Conditional Instruction Execution ' , Computer Architecture News , vol. 19 , no. 1 , pp. 135-142 .
dc.identifier.issn0163-5964
dc.identifier.otherPURE: 101167
dc.identifier.otherPURE UUID: f9e71733-fbbe-46e8-a5d2-6ed23a4a8a0a
dc.identifier.otherdspace: 2299/1568
dc.identifier.urihttp://hdl.handle.net/2299/1568
dc.description.abstractIn a recent paper by Smith, Lam and Horowitz [1] the concept of 'boosting' was introduced, where instructions from one of the possible instruction streams following a conditional branch were scheduled by the compiler for execution in the basic block containing the branch itself. This paper describes how code from both instruction streams following a conditional branch can be considered for execution in the basic block containing the branch. Branch conditions are stored in Boolean registers and all instructions are conditionally executed based on the value in a Boolean register. The two instruction streams can therefore be executed on complementary values of the same Boolean register.en
dc.language.isoeng
dc.relation.ispartofComputer Architecture News
dc.titleA Parallel Pipelined Processor with Conditional Instruction Executionen
dc.contributor.institutionSchool of Computer Science
dc.contributor.institutionCentre for Computer Science and Informatics Research
dc.description.statusPeer reviewed
rioxxterms.typeJournal Article/Review
herts.preservation.rarelyaccessedtrue


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