dc.contributor.author | Adams, R.G. | |
dc.contributor.author | Steven, G.B. | |
dc.date.accessioned | 2008-02-05T12:23:18Z | |
dc.date.available | 2008-02-05T12:23:18Z | |
dc.date.issued | 1991 | |
dc.identifier.citation | Adams , R G & Steven , G B 1991 , ' A Parallel Pipelined Processor with Conditional Instruction Execution ' , Computer Architecture News , vol. 19 , no. 1 , pp. 135-142 . | |
dc.identifier.issn | 0163-5964 | |
dc.identifier.other | dspace: 2299/1568 | |
dc.identifier.uri | http://hdl.handle.net/2299/1568 | |
dc.description.abstract | In a recent paper by Smith, Lam and Horowitz [1] the concept of 'boosting' was introduced, where instructions from one of the possible instruction streams following a conditional branch were scheduled by the compiler for execution in the basic block containing the branch itself. This paper describes how code from both instruction streams following a conditional branch can be considered for execution in the basic block containing the branch. Branch conditions are stored in Boolean registers and all instructions are conditionally executed based on the value in a Boolean register. The two instruction streams can therefore be executed on complementary values of the same Boolean register. | en |
dc.format.extent | 595248 | |
dc.language.iso | eng | |
dc.relation.ispartof | Computer Architecture News | |
dc.title | A Parallel Pipelined Processor with Conditional Instruction Execution | en |
dc.contributor.institution | School of Computer Science | |
dc.contributor.institution | Centre for Computer Science and Informatics Research | |
dc.description.status | Peer reviewed | |
rioxxterms.type | Journal Article/Review | |
herts.preservation.rarelyaccessed | true | |