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dc.contributor.authorEgan, C.
dc.contributor.authorSteven, F.L.
dc.contributor.authorSteven, G.B.
dc.date.accessioned2008-02-06T11:48:32Z
dc.date.available2008-02-06T11:48:32Z
dc.date.issued1997
dc.identifier.citationEgan , C , Steven , F L & Steven , G B 1997 , Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture . in In: EUROMICRO 97 'New Frontiers of Information Technology' short communications, Procs of the 23rd Conf . IEEE , pp. 266-271 .
dc.identifier.isbn0-8186-8215-9
dc.identifier.otherPURE: 102650
dc.identifier.otherPURE UUID: b60606cf-7d45-4056-b0eb-b5080baf4171
dc.identifier.otherdspace: 2299/1582
dc.identifier.otherScopus: 0031368728
dc.identifier.urihttp://hdl.handle.net/2299/1582
dc.description.abstractWhile delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the context of a high-performance superscalar architecture that uses aggressive compile-time instruction scheduling.en
dc.language.isoeng
dc.publisherIEEE
dc.relation.ispartofIn: EUROMICRO 97 'New Frontiers of Information Technology' short communications, Procs of the 23rd Conf
dc.titleDelayed branches versus dynamic branch prediction in a high-performance superscalar architectureen
dc.contributor.institutionSchool of Computer Science
rioxxterms.typeOther
herts.preservation.rarelyaccessedtrue


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