| dc.contributor.author | Egan, C. | |
| dc.contributor.author | Steven, F.L. | |
| dc.contributor.author | Steven, G.B. | |
| dc.date.accessioned | 2008-02-06T11:48:32Z | |
| dc.date.available | 2008-02-06T11:48:32Z | |
| dc.date.issued | 1997 | |
| dc.identifier.citation | Egan , C , Steven , F L & Steven , G B 1997 , Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture . in In: EUROMICRO 97 'New Frontiers of Information Technology' short communications, Procs of the 23rd Conf . Institute of Electrical and Electronics Engineers (IEEE) , pp. 266-271 . | |
| dc.identifier.isbn | 0-8186-8215-9 | |
| dc.identifier.other | dspace: 2299/1582 | |
| dc.identifier.uri | http://hdl.handle.net/2299/1582 | |
| dc.description.abstract | While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the context of a high-performance superscalar architecture that uses aggressive compile-time instruction scheduling. | en |
| dc.format.extent | 458795 | |
| dc.language.iso | eng | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | |
| dc.relation.ispartof | In: EUROMICRO 97 'New Frontiers of Information Technology' short communications, Procs of the 23rd Conf | |
| dc.title | Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture | en |
| dc.contributor.institution | School of Computer Science | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
