| dc.contributor.author | Xu, J. | |
| dc.contributor.author | Sotudeh, R. | |
| dc.date.accessioned | 2008-02-06T11:48:56Z | |
| dc.date.available | 2008-02-06T11:48:56Z | |
| dc.date.issued | 2005 | |
| dc.identifier.citation | Xu , J & Sotudeh , R 2005 , Memory management in output-buffering packet-switch design . in Int Symp on Signals Circuits and Systems 2005 (ISSCS 2005) 1 . Institute of Electrical and Electronics Engineers (IEEE) , pp. 391-394 . https://doi.org/10.1109/ISSCS.2005.1509938 | |
| dc.identifier.other | PURE: 114083 | |
| dc.identifier.other | PURE UUID: dfe68d84-f63c-4023-a6ec-3c1a338c5d7a | |
| dc.identifier.other | dspace: 2299/1583 | |
| dc.identifier.other | Scopus: 33749065510 | |
| dc.identifier.uri | http://hdl.handle.net/2299/1583 | |
| dc.description | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. --Original article can be found at: http://ieeexplore.ieee.org/xpl/RecentCon.jsppunumber=10072 | |
| dc.description.abstract | The most pressing problem in design of a synchronous buffer-memory system in high-speed packet switches is memory bandwidth. If there are multiple packets heading for the same buffer while the buffer cannot consume them simultaneously, some of the packets will have to be dropped. Two approaches are explored to resolve this problem in this paper. One is via improving the buffer-memory architecture, and the other is via replacing clock-based synchronous technology with handshaking-based asynchronous technology. Both approaches are implemented and the results of experiments run to evaluate several aspects of the implementations are compared. | en |
| dc.language.iso | eng | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | |
| dc.relation.ispartof | Int Symp on Signals Circuits and Systems 2005 (ISSCS 2005) 1 | |
| dc.title | Memory management in output-buffering packet-switch design | en |
| dc.contributor.institution | School of Engineering and Technology | |
| rioxxterms.versionofrecord | https://doi.org/10.1109/ISSCS.2005.1509938 | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
