| dc.contributor.author | Findlay, P. | |
| dc.contributor.author | Trainis, S.A. | |
| dc.contributor.author | Steven, G.B. | |
| dc.contributor.author | Adams, R.G. | |
| dc.date.accessioned | 2008-02-12T16:38:23Z | |
| dc.date.available | 2008-02-12T16:38:23Z | |
| dc.date.issued | 1991 | |
| dc.identifier.citation | Findlay , P , Trainis , S A , Steven , G B & Adams , R G 1991 , HARP: a VLIW RISC processor . in In: Procs of 5th Annual European Computer Conference, CompEuro'91 . Institute of Electrical and Electronics Engineers (IEEE) , pp. 368-372 . https://doi.org/10.1109/CMPEUR.1991.257412 | |
| dc.identifier.isbn | 0-8186-2141-9 | |
| dc.identifier.other | PURE: 93536 | |
| dc.identifier.other | PURE UUID: 17be7a13-535b-4284-a399-e5a897eaa259 | |
| dc.identifier.other | dspace: 2299/1604 | |
| dc.identifier.other | Scopus: 0026407866 | |
| dc.identifier.uri | http://hdl.handle.net/2299/1604 | |
| dc.description | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. DOI : 10.1109/CMPEUR.1991.257412 | |
| dc.description.abstract | HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced Instruction Set Computer) processor capable of a sustained instruction execution rate in excess of one instruction per cycle by the parallel execution of RISC type instructions. | en |
| dc.language.iso | eng | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | |
| dc.relation.ispartof | In: Procs of 5th Annual European Computer Conference, CompEuro'91 | |
| dc.title | HARP: a VLIW RISC processor | en |
| dc.contributor.institution | School of Computer Science | |
| dc.contributor.institution | Enterprise and Business Development | |
| dc.contributor.institution | Centre for Computer Science and Informatics Research | |
| dc.contributor.institution | School of Physics, Engineering & Computer Science | |
| rioxxterms.versionofrecord | https://doi.org/10.1109/CMPEUR.1991.257412 | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
