Show simple item record

dc.contributor.authorAhmad, Z.
dc.contributor.authorSotudeh, R.
dc.contributor.authorAkbar Hussain, D.M.
dc.contributor.authorShahab-ud-din, Missing
dc.date.accessioned2016-03-03T12:27:17Z
dc.date.available2016-03-03T12:27:17Z
dc.date.issued2011-01-01
dc.identifier.citationAhmad , Z , Sotudeh , R , Akbar Hussain , D M & Shahab-ud-din , M 2011 , FPGA based intelligent co-operative processor in memory architecture . in IMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011 . vol. 1 , IAENG, International Association of Engineers , pp. 298-302 , IMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011 , Hong Kong , 16/03/11 . < http://www.iaeng.org/IMECS2011/conferences.html >
dc.identifier.citationconference
dc.identifier.isbn978-988182103-4
dc.identifier.urihttp://hdl.handle.net/2299/16670
dc.descriptionCopyright International Association of Engineers
dc.description.abstractIn a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potential benefits of PIM, a concept of Co-operative Intelligent Memory (CIM) was developed by the intelligent system group of University of Hertfordshire, based on the previously developed Co-operative Pseudo Intelligent Memory (CPIM). This paper provides an overview on previous works (CPIM, CIM) and realization of CPIM over two scenarios, cumulative successive addition, and non-cumulative successive addition, using Nexar 2004 EDS tool as a design environment to target device (SPARTAN II, XC2S300E-6PQ208C). The performance (speedup) is then measured against an SISD without significant performance acceleration methods to ensure a speedup assessment obtained against base-line architecture.en
dc.format.extent5
dc.format.extent285240
dc.language.isoeng
dc.publisherIAENG, International Association of Engineers
dc.relation.ispartofIMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011
dc.subjectCo-operative intelligent memory (CIM)
dc.subjectCPU-major
dc.subjectCPU-minor
dc.subjectobserver
dc.subjectprocessor-in-memory (PIM)
dc.subjectshared memory
dc.subjecttask optimizer
dc.titleFPGA based intelligent co-operative processor in memory architectureen
dc.contributor.institutionSchool of Engineering and Technology
dc.contributor.institutionScience & Technology Research Institute
dc.identifier.urlhttp://www.scopus.com/inward/record.url?scp=79960598021&partnerID=8YFLogxK
dc.identifier.urlhttp://www.iaeng.org/IMECS2011/conferences.html
rioxxterms.typeOther
herts.preservation.rarelyaccessedtrue


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record