dc.contributor.author | Ahmad, Z. | |
dc.contributor.author | Sotudeh, R. | |
dc.contributor.author | Akbar Hussain, D.M. | |
dc.contributor.author | Shahab-ud-din, Missing | |
dc.date.accessioned | 2016-03-03T12:27:17Z | |
dc.date.available | 2016-03-03T12:27:17Z | |
dc.date.issued | 2011-01-01 | |
dc.identifier.citation | Ahmad , Z , Sotudeh , R , Akbar Hussain , D M & Shahab-ud-din , M 2011 , FPGA based intelligent co-operative processor in memory architecture . in IMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011 . vol. 1 , IAENG, International Association of Engineers , pp. 298-302 , IMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011 , Hong Kong , 16/03/11 . < http://www.iaeng.org/IMECS2011/conferences.html > | |
dc.identifier.citation | conference | |
dc.identifier.isbn | 978-988182103-4 | |
dc.identifier.uri | http://hdl.handle.net/2299/16670 | |
dc.description | Copyright International Association of Engineers | |
dc.description.abstract | In a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potential benefits of PIM, a concept of Co-operative Intelligent Memory (CIM) was developed by the intelligent system group of University of Hertfordshire, based on the previously developed Co-operative Pseudo Intelligent Memory (CPIM). This paper provides an overview on previous works (CPIM, CIM) and realization of CPIM over two scenarios, cumulative successive addition, and non-cumulative successive addition, using Nexar 2004 EDS tool as a design environment to target device (SPARTAN II, XC2S300E-6PQ208C). The performance (speedup) is then measured against an SISD without significant performance acceleration methods to ensure a speedup assessment obtained against base-line architecture. | en |
dc.format.extent | 5 | |
dc.format.extent | 285240 | |
dc.language.iso | eng | |
dc.publisher | IAENG, International Association of Engineers | |
dc.relation.ispartof | IMECS 2011 - International MultiConference of Engineers and Computer Scientists 2011 | |
dc.subject | Co-operative intelligent memory (CIM) | |
dc.subject | CPU-major | |
dc.subject | CPU-minor | |
dc.subject | observer | |
dc.subject | processor-in-memory (PIM) | |
dc.subject | shared memory | |
dc.subject | task optimizer | |
dc.title | FPGA based intelligent co-operative processor in memory architecture | en |
dc.contributor.institution | School of Engineering and Technology | |
dc.contributor.institution | Science & Technology Research Institute | |
dc.identifier.url | http://www.scopus.com/inward/record.url?scp=79960598021&partnerID=8YFLogxK | |
dc.identifier.url | http://www.iaeng.org/IMECS2011/conferences.html | |
rioxxterms.type | Other | |
herts.preservation.rarelyaccessed | true | |