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        Fixed pattern noise reduction and linearity improvement in time-mode CMOS image sensors

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        sensors_20_05921_v2.pdf (PDF, 3Mb)
        Author
        Kłosowski, Miron
        Sun, Yichuang
        Attention
        2299/23325
        Abstract
        In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128 pixel CMOS imager. Reduction of the PRNU to ∼0.5 LSB has been achieved. Linearity improvement technique has also been proposed which allows for integral non-linearity (INL) reduction to ∼0.5 LSB. Measurements confirm the proposed approach.
        Publication date
        2020-10-20
        Published in
        Sensors
        Published version
        https://doi.org/10.3390/s20205921
        Other links
        http://hdl.handle.net/2299/23325
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