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dc.contributor.authorZhao, Jing
dc.contributor.authorSun, Yichuang
dc.contributor.authorNie, Guigen
dc.contributor.authorSimpson, Oluyomi
dc.contributor.authorXu, Weilin
dc.date.accessioned2021-02-02T10:32:19Z
dc.date.available2021-02-02T10:32:19Z
dc.date.issued2020-11-18
dc.identifier.citationZhao , J , Sun , Y , Nie , G , Simpson , O & Xu , W 2020 , ' Low-power, high-linearity transconductor with a high tolerance for process and temperature variations ' , IET Circuits, Devices & Systems , vol. 14 , no. 8 , pp. 1295-1304 . https://doi.org/10.1049/iet-cds.2019.0565
dc.identifier.issn1751-858X
dc.identifier.otherPURE: 22522276
dc.identifier.otherPURE UUID: 55995534-775e-41a6-af45-40d3d13785e1
dc.identifier.otherScopus: 85097963460
dc.identifier.urihttp://hdl.handle.net/2299/23832
dc.descriptionFunding Information: This research was supported by the Major State Basic Research Development Programme of China (2018YFE0206500). Publisher Copyright: © The Institution of Engineering and Technology 2020. This is the peer reviewed version of the following article: Zhao, J., Sun, Y., Nie, G., Simpson, O. and Xu, W. (2020), Low‐power, high‐linearity transconductor with a high tolerance for process and temperature variations. IET Circuits Devices Syst., 14: 1295-1304. https://doi.org/10.1049/iet-cds.2019.0565. This article may be used for non-commercial purposes in accordance with Wiley Terms and Conditions for Use of Self-Archived Versions.
dc.description.abstractA novel scheme for tunable complementary metal–oxide–semiconductor (CMOS) transconductor robust against process and temperature (PT) variations is presented. The proposed configuration is a voltage controlled circuit based on a double negative channel-metal-oxide-semiconductor (NMOS) transistor differential pairs connected in parallel, which has low power and high linearity. The PT compensation is completed by two identical PT compensation bias voltage generators (PTCBVGs), which can guarantee the designed transconductor high tolerance for PT variations. A complete CMOS transconductor with PTCBVG has been designed and simulated using 0.18 μm technology. The effectiveness of PT compensation technique is proved. The simulation results of post-layout are commensurate with pre-layout. Post-layout simulation results show that when temperature changes from - 40 to 85°C for different process corners (TT, SS, SF, FS and FF), the transconductance varies from 91.8 to 123.6 μS, the temperature coefficient is <1090 ppm/°C, the total harmonic distortion is from - 78 to -72dB at 1 MHz for 0.2 V PP input signal, -3 dB bandwidth changes from 2.5 to 5 GHz, input-referred noise varies from 78.1 to 124.8 nV/sqartHz at 1 MHz and DC power is from 1.5 to 3.2 mW.en
dc.format.extent10
dc.language.isoeng
dc.relation.ispartofIET Circuits, Devices & Systems
dc.rightsEmbargoed
dc.subjectControl and Systems Engineering
dc.subjectElectrical and Electronic Engineering
dc.titleLow-power, high-linearity transconductor with a high tolerance for process and temperature variationsen
dc.contributor.institutionCentre for Engineering Research
dc.contributor.institutionCommunications and Intelligent Systems
dc.contributor.institutionSchool of Physics, Engineering & Computer Science
dc.contributor.institutionDepartment of Engineering and Technology
dc.description.statusPeer reviewed
dc.identifier.urlhttp://www.scopus.com/inward/record.url?scp=85097963460&partnerID=8YFLogxK
dc.relation.schoolSchool of Physics, Engineering & Computer Science
dc.description.versiontypeFinal Accepted Version
dcterms.dateAccepted2020-11-18
rioxxterms.versionAM
rioxxterms.versionofrecordhttps://doi.org/10.1049/iet-cds.2019.0565
rioxxterms.licenseref.uriUnspecified
rioxxterms.typeJournal Article/Review
herts.preservation.rarelyaccessedtrue
herts.rights.accesstypeEmbargoed


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