Low-power, high-linearity transconductor with a high tolerance for process and temperature variations

Abstract

A novel scheme for tunable complementary metal–oxide–semiconductor (CMOS) transconductor robust against process and temperature (PT) variations is presented. The proposed configuration is a voltage controlled circuit based on a double negative channel-metal-oxide-semiconductor (NMOS) transistor differential pairs connected in parallel, which has low power and high linearity. The PT compensation is completed by two identical PT compensation bias voltage generators (PTCBVGs), which can guarantee the designed transconductor high tolerance for PT variations. A complete CMOS transconductor with PTCBVG has been designed and simulated using 0.18 μm technology. The effectiveness of PT compensation technique is proved. The simulation results of post-layout are commensurate with pre-layout. Post-layout simulation results show that when temperature changes from - 40 to 85°C for different process corners (TT, SS, SF, FS and FF), the transconductance varies from 91.8 to 123.6 μS, the temperature coefficient is <1090 ppm/°C, the total harmonic distortion is from - 78 to -72dB at 1 MHz for 0.2 V PP input signal, -3 dB bandwidth changes from 2.5 to 5 GHz, input-referred noise varies from 78.1 to 124.8 nV/sqartHz at 1 MHz and DC power is from 1.5 to 3.2 mW.