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dc.contributor.authorAlawneh, Tareq A.
dc.contributor.authorKirner, Raimund
dc.contributor.authorMenon, Catherine
dc.date.accessioned2021-05-24T16:00:01Z
dc.date.available2021-05-24T16:00:01Z
dc.date.issued2021-05-13
dc.identifier.citationAlawneh , T A , Kirner , R & Menon , C 2021 , Dynamic Row Activation Mechanism for Multi-Core Systems . in CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers . The Association for Computing Machinery , pp. 21-29 , 18th ACM International Conference on Computing Frontiers 2021 (CF 2021) , Italy , 11/05/21 . https://doi.org/10.1145/3457388.3458660
dc.identifier.citationconference
dc.identifier.otherPURE: 24902198
dc.identifier.otherPURE UUID: 7f47106d-f8eb-4725-8840-550c7a8fed67
dc.identifier.otherORCID: /0000-0003-2072-5845/work/95373567
dc.identifier.urihttp://hdl.handle.net/2299/24525
dc.description© 2021 by the Association for Computing Machinery, Inc. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1145/3457388.3458660
dc.description.abstractThe power that stems from modern DRAM devices represents a sig- nificant portion of the overall system power in modern computing systems. In multi-core systems, the competing cores share the same memory banks. The memory contention between these cores may lead to activate a large DRAM row only to access a small portion of data. This row over-fetching problem wastes a significant DRAM activation power with a slight performance gain. In this paper, we propose a dynamic row activation mechanism, in which the optimal size of DRAM rows is detected at run-time based on monitoring the behavioural changes of the memory re- quests in accessing sub-rows. The proposed mechanism aims at providing significant memory power savings, reducing the average memory access latency, and maintaining the full DRAM bandwidth. Our experimental results using four-core multi-programming work- loads revealed that the proposed mechanism in this study can achieve both significant memory power reduction and average DRAM memory access latency improvement with negligible area overhead.en
dc.format.extent9
dc.language.isoeng
dc.publisherThe Association for Computing Machinery
dc.relation.ispartofCF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers
dc.titleDynamic Row Activation Mechanism for Multi-Core Systemsen
dc.contributor.institutionCentre for Computer Science and Informatics Research
dc.contributor.institutionSchool of Physics, Engineering & Computer Science
dc.contributor.institutionDepartment of Computer Science
dc.contributor.institutionCentre for Future Societies Research
dc.relation.school
dcterms.dateAccepted2021-05-13
rioxxterms.versionAM
rioxxterms.versionofrecordhttps://doi.org/10.1145/3457388.3458660
rioxxterms.typeOther
herts.preservation.rarelyaccessedtrue


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