dc.contributor.author | Alawneh, Tareq A. | |
dc.contributor.author | Kirner, Raimund | |
dc.contributor.author | Menon, Catherine | |
dc.date.accessioned | 2021-05-24T16:00:01Z | |
dc.date.available | 2021-05-24T16:00:01Z | |
dc.date.issued | 2021-05-13 | |
dc.identifier.citation | Alawneh , T A , Kirner , R & Menon , C 2021 , Dynamic Row Activation Mechanism for Multi-Core Systems . in CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers . ACM Press , pp. 21-29 , 18th ACM International Conference on Computing Frontiers 2021 (CF 2021) , Italy , 11/05/21 . https://doi.org/10.1145/3457388.3458660 | |
dc.identifier.citation | conference | |
dc.identifier.other | ORCID: /0000-0003-2072-5845/work/95373567 | |
dc.identifier.uri | http://hdl.handle.net/2299/24525 | |
dc.description | © 2021 by the Association for Computing Machinery, Inc. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1145/3457388.3458660 | |
dc.description.abstract | The power that stems from modern DRAM devices represents a sig- nificant portion of the overall system power in modern computing systems. In multi-core systems, the competing cores share the same memory banks. The memory contention between these cores may lead to activate a large DRAM row only to access a small portion of data. This row over-fetching problem wastes a significant DRAM activation power with a slight performance gain. In this paper, we propose a dynamic row activation mechanism, in which the optimal size of DRAM rows is detected at run-time based on monitoring the behavioural changes of the memory re- quests in accessing sub-rows. The proposed mechanism aims at providing significant memory power savings, reducing the average memory access latency, and maintaining the full DRAM bandwidth. Our experimental results using four-core multi-programming work- loads revealed that the proposed mechanism in this study can achieve both significant memory power reduction and average DRAM memory access latency improvement with negligible area overhead. | en |
dc.format.extent | 9 | |
dc.format.extent | 793786 | |
dc.language.iso | eng | |
dc.publisher | ACM Press | |
dc.relation.ispartof | CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers | |
dc.title | Dynamic Row Activation Mechanism for Multi-Core Systems | en |
dc.contributor.institution | Centre for Computer Science and Informatics Research | |
dc.contributor.institution | School of Physics, Engineering & Computer Science | |
dc.contributor.institution | Department of Computer Science | |
dc.contributor.institution | Centre for Future Societies Research | |
rioxxterms.versionofrecord | 10.1145/3457388.3458660 | |
rioxxterms.type | Other | |
herts.preservation.rarelyaccessed | true | |