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dc.contributor.authorChen, Lisheng
dc.contributor.authorChen, Lang
dc.contributor.authorGe, Zeyu
dc.contributor.authorSun, Yichuang
dc.contributor.authorHamilton, Tara
dc.contributor.authorZhu, Xi
dc.date.accessioned2021-09-01T13:45:02Z
dc.date.available2021-09-01T13:45:02Z
dc.date.issued2021-08-25
dc.identifier.citationChen , L , Chen , L , Ge , Z , Sun , Y , Hamilton , T & Zhu , X 2021 , ' A 90-GHz Asymmetrical Single-Pole Double-Throw Switch with >19.5-dBm 1-dB Compression Point in Transmission Mode Using 55-nm Bulk CMOS Technology ' , IEEE Transactions on Circuits and Systems I: Regular Papers . https://doi.org/10.1109/TCSI.2021.3106231
dc.identifier.issn1549-8328
dc.identifier.otherPURE: 25777100
dc.identifier.otherPURE UUID: 4da3ffe9-dc37-499a-9012-c0f1ce31dea3
dc.identifier.otherScopus: 85113858546
dc.identifier.urihttp://hdl.handle.net/2299/25033
dc.description© Copyright 2021 IEEE. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2021.3106231
dc.description.abstractThe millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2.en
dc.language.isoeng
dc.relation.ispartofIEEE Transactions on Circuits and Systems I: Regular Papers
dc.titleA 90-GHz Asymmetrical Single-Pole Double-Throw Switch with >19.5-dBm 1-dB Compression Point in Transmission Mode Using 55-nm Bulk CMOS Technologyen
dc.contributor.institutionCentre for Engineering Research
dc.contributor.institutionCommunications and Intelligent Systems
dc.contributor.institutionSchool of Physics, Engineering & Computer Science
dc.contributor.institutionDepartment of Engineering and Technology
dc.description.statusPeer reviewed
rioxxterms.versionAM
rioxxterms.versionofrecordhttps://doi.org/10.1109/TCSI.2021.3106231
rioxxterms.typeJournal Article/Review
herts.preservation.rarelyaccessedtrue


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