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dc.contributor.authorChen, Lang
dc.contributor.authorChen, Lisheng
dc.contributor.authorGe, Zeyu
dc.contributor.authorSun, Yichuang
dc.contributor.authorZhu, Xi
dc.date.accessioned2023-06-15T15:00:01Z
dc.date.available2023-06-15T15:00:01Z
dc.date.issued2023-06-08
dc.identifier.citationChen , L , Chen , L , Ge , Z , Sun , Y & Zhu , X 2023 , ' A 40-GHz Load Modulated Balanced Power Amplifier using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS ' , IEEE Transactions on Circuits and Systems I: Regular Papers . https://doi.org/10.1109/TCSI.2023.3282731
dc.identifier.issn1549-8328
dc.identifier.urihttp://hdl.handle.net/2299/26434
dc.description© 2023 IEEE - All rights reserved. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2023.3282731 ​​​​​​​
dc.description.abstractIn this work, a ten-way power-combined poweramplifier is designed using a load modulated balanced amplifier(LMBA)-based architecture. To provide the required magnitudeand phase controls between the main and control-signal paths ofthe LMBA, an unequal power splitter and a phase compensationnetwork are proposed. As proof of concept, the designed poweramplifier is implemented in a 45-nm SOI CMOS process. At 40GHz, it delivers a 25.1 dBm Psat with a peak power-addedefficiency (PAE) of 27.9%. At 6-dB power back-off level, itachieves 1.39 times drain efficiency enhancement over an idealClass-B power amplifier. Using a 200-MHz single-carrier 64-QAMsignal, the designed amplifier delivers an average output power of16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB andACPR of -25.3 dBc. The die size, including all testing pads, is only1.92 mm2. To the best of the authors’ knowledge, compared withthe other recently published silicon-based LMBAs, this designachieves the highest Psat.en
dc.format.extent9
dc.format.extent3489596
dc.language.isoeng
dc.relation.ispartofIEEE Transactions on Circuits and Systems I: Regular Papers
dc.titleA 40-GHz Load Modulated Balanced Power Amplifier using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOSen
dc.contributor.institutionSchool of Physics, Engineering & Computer Science
dc.contributor.institutionDepartment of Engineering and Technology
dc.contributor.institutionCentre for Engineering Research
dc.contributor.institutionCentre for Future Societies Research
dc.contributor.institutionCommunications and Intelligent Systems
dc.description.statusPeer reviewed
rioxxterms.versionofrecord10.1109/TCSI.2023.3282731
rioxxterms.typeJournal Article/Review
herts.preservation.rarelyaccessedtrue


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