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dc.contributor.authorSteven, G.B.
dc.contributor.authorGray, S.M.
dc.contributor.authorAdams, R.G.
dc.identifier.citationSteven , G B , Gray , S M & Adams , R G 1989 , ' HARP: A Parallel Pipelined RISC Processor ' , Microprocessors and Microsystems , vol. 13 , no. 9 , pp. 579-587 .
dc.identifier.otherPURE: 89249
dc.identifier.otherPURE UUID: b7b10415-3942-41a0-aff9-d75462e72615
dc.identifier.otherdspace: 2299/3720
dc.identifier.otherScopus: 0024764807
dc.descriptionOriginal article can be found at: Copyright Elsevier B.V. [Full text of this article is not available in the UHRA]
dc.description.abstractHARP (the Hatfield RISC processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a RISC processor capable of a sustained instruction execution rate in excess of one instruction per cycle. Investigations to date support the hypothesis that this goal can be achieved by the development of an integrated processor-compiler pair in which the processor is specifically designed to support low-level parallelism identified by the compiler. This paper describes the HARP architectural model and discusses those features which support parallel instruction execution. Parallelism is provided in the hardware by multiple instruction pipelines which execute independent RISC-like instructions simultaneously. The principal techniques employed to exploit the available parallelism are efficient pipelining, register bypassing, optional register writeback and conditional execution of instructions. Examples are given which illustrate the effectiveness of these techniques in increasing the performance of HARP.en
dc.relation.ispartofMicroprocessors and Microsystems
dc.titleHARP: A Parallel Pipelined RISC Processoren
dc.contributor.institutionSchool of Computer Science
dc.contributor.institutionCentre for Computer Science and Informatics Research
dc.description.statusPeer reviewed
rioxxterms.typeJournal Article/Review

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