Addressing Mechanisms for VLIW and Superscalar Processors

Abstract

RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further simplifying the addressing modes. In particular, the distinctive ORed indexing addressing mechanism employed by the HARP VLIW processor boosts performance by 10%. Register indirect addressing on its own yields a similar performance improvement.