Address and data register separation of the M68000 family
On the M68000 registers are partitioned into eight data registers and eight address registers. Many authors consider this division to be a breakdown in instruction set orthogonality and a major shortcoming of the M68000 architecture. However, an investigation at Hatfield Polytechnic into the impact of instruction set orthogonality on compiler code generation found that, in practice, this register division was not a problem. FLEC, and Hatfield Polytechnic research compiler, which compiles a subset of Modula-2 onto the M68000, was written to assist in this investigation. Our observations are derived from our experience while writing FLEC.