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dc.contributor.authorAdams, R.G.
dc.contributor.authorGray, S.M.
dc.contributor.authorSteven, G.B.
dc.date.accessioned2010-08-17T09:07:52Z
dc.date.available2010-08-17T09:07:52Z
dc.date.issued1994
dc.identifier.citationAdams , R G , Gray , S M & Steven , G B 1994 , HARP: a statically scheduled multiple-instruction-issue architecture and its compiler . UH Computer Science Technical Report , vol. 163 , University of Hertfordshire .
dc.identifier.otherPURE: 98648
dc.identifier.otherPURE UUID: e419d312-7a9f-468a-b610-478d6b087876
dc.identifier.otherdspace: 2299/4781
dc.identifier.urihttp://hdl.handle.net/2299/4781
dc.descriptionSubmitted to 2nd Euromicro Workshop on Parallel and Distributed Processing, Spain, 1994
dc.description.abstractThis paper presents the results of an investigation into the performance of a new statically scheduled multiple-instruction-issue architecture and its compiler. HARP is a Long Instruction Word Architecture developed in conjunction with a simple compile-time scheduling technique called conditional compaction. The architecture is characterised by a conditional execution mechanism which is used by the scheduler to pack the instructions within a procedure into long instruction words. The study compares the speedups obtained for the C and Modula-2 versions of a set of short, general purpose, integer benchmarks, running on simulations of the architecture with different functional unit configurations.en
dc.language.isoeng
dc.publisherUniversity of Hertfordshire
dc.relation.ispartofseriesUH Computer Science Technical Report
dc.rightsOpen
dc.titleHARP: a statically scheduled multiple-instruction-issue architecture and its compileren
dc.contributor.institutionSchool of Computer Science
dc.relation.schoolSchool of Computer Science
dcterms.dateAccepted1994
rioxxterms.typeOther
herts.preservation.rarelyaccessedtrue
herts.rights.accesstypeOpen


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