| dc.contributor.author | Adams, R.G. | |
| dc.contributor.author | Gray, S.M. | |
| dc.contributor.author | Steven, G.B. | |
| dc.date.accessioned | 2010-08-17T09:07:52Z | |
| dc.date.available | 2010-08-17T09:07:52Z | |
| dc.date.issued | 1994 | |
| dc.identifier.citation | Adams , R G , Gray , S M & Steven , G B 1994 , HARP: a statically scheduled multiple-instruction-issue architecture and its compiler . UH Computer Science Technical Report , vol. 163 , University of Hertfordshire . | |
| dc.identifier.other | dspace: 2299/4781 | |
| dc.identifier.uri | http://hdl.handle.net/2299/4781 | |
| dc.description | Submitted to 2nd Euromicro Workshop on Parallel and Distributed Processing, Spain, 1994 | |
| dc.description.abstract | This paper presents the results of an investigation into the performance of a new statically scheduled multiple-instruction-issue architecture and its compiler. HARP is a Long Instruction Word Architecture developed in conjunction with a simple compile-time scheduling technique called conditional compaction. The architecture is characterised by a conditional execution mechanism which is used by the scheduler to pack the instructions within a procedure into long instruction words. The study compares the speedups obtained for the C and Modula-2 versions of a set of short, general purpose, integer benchmarks, running on simulations of the architecture with different functional unit configurations. | en |
| dc.format.extent | 2177983 | |
| dc.language.iso | eng | |
| dc.publisher | University of Hertfordshire | |
| dc.relation.ispartofseries | UH Computer Science Technical Report | |
| dc.title | HARP: a statically scheduled multiple-instruction-issue architecture and its compiler | en |
| dc.contributor.institution | School of Computer Science | |
| dc.contributor.institution | Centre for Computer Science and Informatics Research | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
