Developing a simulator for the Hatfield Superscalar processor

Abstract

Researchers at the University of Hertfordshire's department of Computer Science are currently investigating the possibility of scheduling code at compile time for a new family of superscalar processors. This project has two main elements, the first being the specification of the architectural model for the superscalar processors and the development of a parametrised Superscalar Simulator program. The second element is an Instruction Scheduler program that will apply a global scheduling algorithm to the superscalar source assembly code. The overall objective of the project is increase and exploit the amount of instruction-level parallelism available by applying scheduling techniques at compile time, rather than by using the processor's hardware at run time. This report deals specifically with the design and development of the Superscalar Simulator program and gives a detailed explanation of the main features of the architectural model adopted.