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dc.contributor.authorElston, C.J.
dc.date.accessioned2010-09-28T13:44:04Z
dc.date.available2010-09-28T13:44:04Z
dc.date.issued1994
dc.identifier.citationElston , C J 1994 , Potential for asynchronous microprocessor design . UH Computer Science Technical Report , vol. 182 , University of Hertfordshire .
dc.identifier.otherPURE: 99670
dc.identifier.otherPURE UUID: c6220cd5-4cb8-454f-a525-eb6f24dbd8af
dc.identifier.otherdspace: 2299/4851
dc.identifier.urihttp://hdl.handle.net/2299/4851
dc.description.abstractAsynchronous (non-globally clocked) design and realisation of processors is undergoing a resurgence of interest. The difficulties of producing complex, high performance synchronous (globally clocked) processors are becoming severe and these problems will only be compounded by technological advancement. Asynchronous design has its own associated difficulties in producing functionally correct, high performance processors but there is the potential to increase performance and simplify design. This report outlines a number of promising approaches to asynchronous design giving the advantages and disadvantages of each in the context of present and future environments.en
dc.language.isoeng
dc.publisherUniversity of Hertfordshire
dc.relation.ispartofseriesUH Computer Science Technical Report
dc.rights/dk/atira/pure/core/openaccesspermission/open
dc.subjectmicroprocessor design
dc.subjectasynchronous systems
dc.subjectdelay-insensitive circuits
dc.subjectapeed-independent circuits
dc.subjectmicropipelines
dc.titlePotential for asynchronous microprocessor designen
dc.contributor.institutionSchool of Computer Science
dc.relation.schoolSchool of Computer Science
rioxxterms.typeOther
herts.preservation.rarelyaccessedtrue
herts.rights.accesstyperestrictedAccess


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