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dc.contributor.authorElston, C.J.
dc.contributor.authorChristianson, B.
dc.contributor.authorFindlay, P.
dc.contributor.authorSteven, G.B.
dc.date.accessioned2010-11-04T14:55:37Z
dc.date.available2010-11-04T14:55:37Z
dc.date.issued1995
dc.identifier.citationElston , C J , Christianson , B , Findlay , P & Steven , G B 1995 , Hades - towards the design of an asynchronous superscalar processor . UH Computer Science Technical Report , vol. 218 , University of Hertfordshire .
dc.identifier.otherPURE: 97855
dc.identifier.otherPURE UUID: 24f41664-c076-4a72-a101-de2e291697e4
dc.identifier.otherdspace: 2299/4961
dc.identifier.otherScopus: 0029233251
dc.identifier.urihttp://hdl.handle.net/2299/4961
dc.description.abstractHades is a processor architecture aimed at single and multiple-instruction-issue asynchronous implementations. This paper uses a baseline version of Hades to illustrate some of the difficulties encountered in asynchronous processor design and demonstrates why it is undesirable to design a processor which is simply an asynchronous version of an existing synchronous processor. Particular emphasis is placed on an explicitly declared delayed branch mechanism and a decoupled register forwarding mechanism developed for Hades. Ths branch mechanism allows instruction fetching to proceed while branch instructions are being resolved, while the forwarding mechanism allows the last result of each functional unit to be bypassed to following instructions, yet completely separates bypassing from the register write back operation.en
dc.language.isoeng
dc.publisherUniversity of Hertfordshire
dc.relation.ispartofseriesUH Computer Science Technical Report
dc.titleHades - towards the design of an asynchronous superscalar processoren
dc.contributor.institutionSchool of Computer Science
dc.contributor.institutionCentre for Computer Science and Informatics Research
dc.contributor.institutionEnterprise and Business Development
rioxxterms.typeOther
herts.preservation.rarelyaccessedtrue


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