Developing the Hatfield Superscalar architecture cache simulator

Abstract

A great deal of the current research into computer architecture is directed at Multiple Instruction Issue (MII) processors. These processors have the ability to issue, process and retire more than one instruction per cycle. Multiple instructions can be simultaneously issued when there are no dependencies between them. MII architectures can be split into two diverse types: VLIW and superscalar. These types are differentiated by the time at which the instructions are scheduled into groups that could be issued in parallel. A VLIW processor relies on the complier to generate fixed sized groups of instructions, while a superscalar processor relies on the processor to dynamically generate groups of independent instructions. Current work at the University of Hertfordshire is focused on developing a processor that combines the best features of both VLIW and superscalar processors.