dc.contributor.author | Tate, D. | |
dc.date.accessioned | 2011-02-22T14:18:38Z | |
dc.date.available | 2011-02-22T14:18:38Z | |
dc.date.issued | 1998 | |
dc.identifier.citation | Tate , D 1998 , The impact of a realistic cache structure on a high performance Superscalar architecture . UH Computer Science Technical Report , vol. 319 , University of Hertfordshire . | |
dc.identifier.other | dspace: 2299/5376 | |
dc.identifier.uri | http://hdl.handle.net/2299/5376 | |
dc.description.abstract | Despite the widely held belief that the most limiting factor in processor performance is the memory hierarchy, much of the recent research into multiple instruction issue techniques assumes a perfect cache structure with a 100% hit rate. This paper attempts to rectify this imbalance by quantifying the performance impact of if incorporating a realistic cache structure into a high-performance superscalar architecture. A highly parameterised cache simulator is integrated into a minimal superscalar architecture, the Hatfield Superscalar Architecture (HSA), that uses static instruction scheduling and in-order instruction issue. Two main studies are presented. First, the impact of a cache on unscheduled code is compared to the impact of a cache on scheduled code. Second, the speedup achieved through static instruction scheduling with a perfect cache is compared to the speedup achieved with a series of cache sizes. | en |
dc.format.extent | 4901061 | |
dc.language.iso | eng | |
dc.publisher | University of Hertfordshire | |
dc.relation.ispartofseries | UH Computer Science Technical Report | |
dc.title | The impact of a realistic cache structure on a high performance Superscalar architecture | en |
dc.contributor.institution | School of Computer Science | |
rioxxterms.type | Other | |
herts.preservation.rarelyaccessed | true | |