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dc.contributor.authorBensaali, F.
dc.contributor.authorAmira, A.
dc.contributor.authorSotudeh, R.
dc.date.accessioned2011-03-17T16:26:42Z
dc.date.available2011-03-17T16:26:42Z
dc.date.issued2007
dc.identifier.citationBensaali , F , Amira , A & Sotudeh , R 2007 , ' A general framework for efficient FPGA implementation of matrix product ' , Mediterranean Journal of Computers and Networks , vol. 3 , no. 3 , pp. 124-131 .
dc.identifier.issn1744-2397
dc.identifier.otherPURE: 113385
dc.identifier.otherPURE UUID: aea9ab57-a606-4070-86f9-7e17213747b6
dc.identifier.otherdspace: 2299/5506
dc.identifier.urihttp://hdl.handle.net/2299/5506
dc.descriptionOriginal article can be found at: http://www.medjcn.com/ Copyright Softmotor Limited
dc.description.abstractHigh performance systems are required by the developers for fast processing of computationally intensive applications. Reconfigurable hardware devices in the form of Filed-Programmable Gate Arrays (FPGAs) have been proposed as viable system building blocks in the construction of high performance systems at an economical price. Given the importance and the use of matrix algorithms in scientific computing applications, they seem ideal candidates to harness and exploit the advantages offered by FPGAs. In this paper, a system for matrix algorithm cores generation is described. The system provides a catalog of efficient user-customizable cores, designed for FPGA implementation, ranging in three different matrix algorithm categories: (i) matrix operations, (ii) matrix transforms and (iii) matrix decomposition. The generated core can be either a general purpose or a specific application core. The methodology used in the design and implementation of two specific image processing application cores is presented. The first core is a fully pipelined matrix multiplier for colour space conversion based on distributed arithmetic principles while the second one is a parallel floating-point matrix multiplier designed for 3D affine transformations.en
dc.language.isoeng
dc.relation.ispartofMediterranean Journal of Computers and Networks
dc.rightsOpen
dc.subjectmatrix multiplication
dc.subjectfield programmable gate array
dc.subjectdistributed arithmetic
dc.subject3D affine transformations
dc.titleA general framework for efficient FPGA implementation of matrix producten
dc.contributor.institutionSchool of Engineering and Technology
dc.description.statusPeer reviewed
dc.relation.schoolSchool of Engineering and Technology
dcterms.dateAccepted2007
rioxxterms.typeJournal Article/Review
herts.preservation.rarelyaccessedtrue
herts.rights.accesstypeOpen


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