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dc.contributor.authorDavies, S.J.
dc.contributor.authorElston, C.J.
dc.contributor.authorFindlay, P.
dc.date.accessioned2011-03-22T16:19:45Z
dc.date.available2011-03-22T16:19:45Z
dc.date.issued1999
dc.identifier.citationDavies , S J , Elston , C J & Findlay , P 1999 , Register bypassing in an asynchronous superscalar processor . UH Computer Science Technical Report , vol. 328 , University of Hertfordshire .
dc.identifier.otherdspace: 2299/5519
dc.identifier.urihttp://hdl.handle.net/2299/5519
dc.description.abstractRegister bypassing, universally provided in synchronous processors, is more difficult to implement in an asynchronous design. Asynchronous bypassing requires synchronization between the forwarding and receiving units, with the danger that the advantages of synchronization operation may be nullified by reintroducing the lock-step operation of synchronous processors. We present a novel implementation of register bypassing in an asynchronous processor architecture. Our technique of Decoupled Operand Forwarding provides centralized control over the bypassing operation, yet allows multiple execution units to function asynchronously. Our ideas are presented within the context of the development of Hades, a generic asynchronous processor architecture. We employ single-issue and dual-issue simulations of Hades to quantify the benefits of Decoupled Operand Forwarding and conclude that Decoupled Operand Forwarding yields significant speedups because of its success in removing register files from the critical timing path.en
dc.format.extent2956749
dc.language.isoeng
dc.publisherUniversity of Hertfordshire
dc.relation.ispartofseriesUH Computer Science Technical Report
dc.titleRegister bypassing in an asynchronous superscalar processoren
dc.contributor.institutionSchool of Computer Science
dc.contributor.institutionEnterprise and Business Development
rioxxterms.typeOther
herts.preservation.rarelyaccessedtrue


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