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    • Avoiding timing anomalies using code transformations 

      Kadlec, A.; Kirner, Raimund; Puschner, P. (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Divide-and-conquer approaches to worst-case execution-time analysis (WCET analysis) pose a safety risk when applied to code for complex modern processors: Interferences between the hardware acceleration mechanisms of these ...