Search
Now showing items 1-2 of 2
HARP: a statically scheduled multiple-instruction-issue architecture and its compiler
(University of Hertfordshire, 1994)
This paper presents the results of an investigation into the performance of a new statically scheduled multiple-instruction-issue architecture and its compiler. HARP is a Long Instruction Word Architecture developed in ...
Using conditional execution to exploit instruction level concurrency
(University of Hertfordshire, 1994)
Multiple-instruction-issue processors seek to improve performance over scalar RISC processors by providing multiple pipelined functional units in order to fetch, decode and execute several instructions per cycle. The process ...