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Static instruction scheduling for the HARP multiple-instruction-issue architecture
(University of Hertfordshire, 1992)
HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, ...
iHARP a Multiple Instruction Issue Processor Chip Incorporating RISC and VLIW Design Features
(1992)
RISC (Reduced Instruction Set Computers) processors have established an impressive performance standard by executing one instruction in each processor cycle. More recently, VLIW (Very Long Instruction Word) and superscalar ...