Browsing Research publications by Author "Rossi, Daniele"

Now showing items 1-13 of 13

    • Aging Benefits in Nanometer CMOS Designs 

      Rossi, Daniele; Tenentes, Vasileios; Yang, Sheng; Khursheed, Saqib; Al-Hashimi, Bashir M. (2016-05-02)
      n this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption ...

    • Coarse-grained Online Monitoring of BTI Aging by Reusing Power Gating Infrastructure 

      Tenentes, Vasileios; Rossi, Daniele; Yang, Sheng; Khursheed, Saqib; Al-Hashimi, Bashir M.; Gunn, Steve R. (2017-04-01)
      In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on ...

    • Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories 

      Rossi, Daniele; Tenentes, Vasileios; Reddy, Sudhakar M.; Al-Hashimi, Bashir M.; Brown, Andrew (2017-07-19)
      In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop ...

    • Impact of Aging Phenomena on Latches’ Robustness 

      Omana, Martin; Rossi, Daniele; Edara, TusharaSandeep; Metra, Cecilia (2016-03-08)
      In this paper, we analyze the effects of aging mechanisms on the soft error susceptibility of both standard and robust latches. Particularly, we consider bias temperature instability (BTI) affecting both nMOS (positive ...

    • Impact of Bias Temperature Instability on Soft Error Susceptibility 

      Rossi, Daniele; Omana, Martin; Metra, Cecilia; Paccagnella, Alessandro (2015-04-30)
      In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors ...

    • The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology 

      Halak, Basel; Tenentes, Vasileios; Rossi, Daniele (2016-12-01)
      On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this ...

    • Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs 

      Tenentes, Vasileios; Rossi, Daniele; Khursheed, Saqib; Al-Hashimi, Bashir M.; Chakrabarty, Krishnendu (2018-04-01)
      Manufacturing defects that do not affect the functional operation of low power integrated circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive ...

    • Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST 

      Omana, Martin; Rossi, Daniele; Beniamino, Edda; Metra, Cecilia; Tirumurti, Chandra; Galivanche, Rajesh (2016-08-31)
      During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. ...

    • Low-Cost On-Chip Clock Jitter Measurement Scheme 

      Omana, Martin; Rossi, Daniele; Giaffreda, Daniele; Metra, Cecilia; Mak, TM; Raman, Asifur; Tam, Simon (2015-03-01)
      In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high ...

    • Modeling and Detection of Hotspot in Shaded Photovoltaic Cells 

      Rossi, Daniele; Omana, Martin; Giaffreda, Daniele; Metra, Cecilia (2015-06-01)
      In this paper, we address the problem of modeling the thermal behavior of photovoltaic (PV) cells undergoing a hotspot condition. In case of shading, PV cells may experience a dramatic temperature increase, with consequent ...

    • Reliable Power Gating With NBTI Aging Benefits 

      Rossi, Daniele; Tenentes, Vasileios; Yang, Sheng; Khursheed, Saqib; Al-Hashimi, Bashir M. (2016-02-15)
      In this paper, we show that negative bias temperature instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT), presents considerable benefits for ...

    • Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 

      Omana, Martin; Rossi, Daniele; Fuzzi, Filippo; Metra, Cecilia; Tirumurti, Chandra; Galivanche, Rajesh (2017-01-31)
      The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of ...

    • Susceptible Workload Evaluation and Protection using Selective Fault Tolerance 

      Gutierrez, Mauricio D.; Tenentes, Vasileios; Rossi, Daniele; Kazmierski, Tom J. (2017-06-20)
      Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in ...