Browsing Research publications by Author "Trainis, S.A."

Now showing items 1-4 of 4

    • The development of iHARP: a multiple instruction issue processor chip 

      Steven, G.B.; Adams, R.G.; Findlay, P.; Trainis, S.A. (Institute of Electrical and Electronics Engineers (IEEE), 1991)
      During the last decade RISC ideas on processor architecture have become widely accepted. RISC architectures achieve significant performance advantages over CISC architectures by striving to execute one instruction per ...

    • HARP: a VLIW RISC processor 

      Findlay, P.; Trainis, S.A.; Steven, G.B.; Adams, R.G. (Institute of Electrical and Electronics Engineers (IEEE), 1991)
      HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced ...

    • iHARP a Multiple Instruction Issue Processor Chip Incorporating RISC and VLIW Design Features 

      Trainis, S.A.; Findlay, P.; Steven, G.B.; Adams, R.G.; McHale, D. (1992)
      RISC (Reduced Instruction Set Computers) processors have established an impressive performance standard by executing one instruction in each processor cycle. More recently, VLIW (Very Long Instruction Word) and superscalar ...

    • iHarp: a Multiple Instruction Issue Processor 

      Steven, G.B.; Adams, R.G.; Findlay, P.; Trainis, S.A. (1992)