Search
Now showing items 1-2 of 2
Developing the Hatfield Superscalar architecture cache simulator
(University of Hertfordshire, 1998)
A great deal of the current research into computer architecture is directed at Multiple Instruction Issue (MII) processors. These processors have the ability to issue, process and retire more than one instruction per cycle. ...
The impact of a realistic cache structure on a high performance Superscalar architecture
(University of Hertfordshire, 1998)
Despite the widely held belief that the most limiting factor in processor performance is the memory hierarchy, much of the recent research into multiple instruction issue techniques assumes a perfect cache structure with ...