Search
Now showing items 1-3 of 3
A Parallel Pipelined Processor with Conditional Instruction Execution
(1991)
In a recent paper by Smith, Lam and Horowitz [1] the concept of 'boosting' was introduced, where instructions from one of the possible instruction streams following a conditional branch were scheduled by the compiler for ...
The development of iHARP: a multiple instruction issue processor chip
(Institute of Electrical and Electronics Engineers (IEEE), 1991)
During the last decade RISC ideas on processor architecture have become widely accepted. RISC architectures achieve significant performance advantages over CISC architectures by striving to execute one instruction per ...
HARP: a VLIW RISC processor
(Institute of Electrical and Electronics Engineers (IEEE), 1991)
HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced ...