| dc.contributor.author | Puschner, P. | |
| dc.contributor.author | Kirner, Raimund | |
| dc.contributor.editor | Nakajima, T. | |
| dc.contributor.editor | Kim, M.H. | |
| dc.date.accessioned | 2011-08-17T09:01:20Z | |
| dc.date.available | 2011-08-17T09:01:20Z | |
| dc.date.issued | 2003 | |
| dc.identifier.citation | Puschner , P & Kirner , R 2003 , Avoiding timing problems in real-time software . in T Nakajima & M H Kim (eds) , Procs of IEEE Workshop on Software Technologies for Future Embedded Systems . Institute of Electrical and Electronics Engineers (IEEE) , pp. 75-78 , IEEE Workshop on Software Technologies for Future Embedded Systems (WSTFES 2003) , HAKODATE , 15/05/03 . https://doi.org/10.1109/WSTFES.2003.1201365 | |
| dc.identifier.citation | conference | |
| dc.identifier.isbn | 0-7695-1937-7 | |
| dc.identifier.uri | http://hdl.handle.net/2299/6273 | |
| dc.description | “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” | |
| dc.description.abstract | To safely establish the correct timing of a real-time processing node, adequate architectural structures have to be used. This refers to the hardware architecture of the processing node as well as the software architecture of its operating system and application software. This paper presents architectures that allow for a well structured and simple timing analysis. First, it presents solutions for cleanly splitting the overall timing analysis into schedulability analysis and task worst-case execution time analysis. Second, it presents a programming strategy that yields software that is highly temporally predictable and easy to analyze for its worst-case execution time. | en |
| dc.format.extent | 4 | |
| dc.format.extent | 35454 | |
| dc.language.iso | eng | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | |
| dc.relation.ispartof | Procs of IEEE Workshop on Software Technologies for Future Embedded Systems | |
| dc.title | Avoiding timing problems in real-time software | en |
| dc.contributor.institution | Centre for Computer Science and Informatics Research | |
| dc.contributor.institution | Department of Computer Science | |
| dc.contributor.institution | School of Physics, Engineering & Computer Science | |
| dc.contributor.institution | Centre for Future Societies Research | |
| rioxxterms.versionofrecord | 10.1109/WSTFES.2003.1201365 | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
