| dc.contributor.author | He, Y. | |
| dc.contributor.author | Jiang, J. | |
| dc.contributor.author | Sun, Y. | |
| dc.date.accessioned | 2011-10-25T10:01:24Z | |
| dc.date.available | 2011-10-25T10:01:24Z | |
| dc.date.issued | 2004 | |
| dc.identifier.citation | He , Y , Jiang , J & Sun , Y 2004 , A 12-bit 150-MHz 1.25-mm2 CMOS DAC . in Procs of the 2004 IEEE Region 10 Conference, TENCON . vol. 4 , Institute of Electrical and Electronics Engineers (IEEE) , pp. 237-240 . https://doi.org/10.1109/TENCON.2004.1414913 | |
| dc.identifier.isbn | 0-7803-8560-8 | |
| dc.identifier.other | dspace: 2299/4754 | |
| dc.identifier.uri | http://hdl.handle.net/2299/6796 | |
| dc.description | “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” | |
| dc.description.abstract | This paper presents a 12-bit 150-MHz current steering DAC with hierarchical symmetrical switching sequence that compensates gradient errors. The circuit of the DAC employs segmented architecture; the least significant bits (LSBs) steer a binary weighted array, while the most significant bits (MSBs) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are ±0.6 LSB and ±0.9 LSB, respectively. The circuit is fabricated in 0.5 μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process. It occupies 1.27 mm×0.96 mm chip area, when operating at 150 MHz and dissipates 91.6 mW from a 5.0 V power supply, which is much smaller. | en |
| dc.format.extent | 1897956 | |
| dc.language.iso | eng | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | |
| dc.relation.ispartof | Procs of the 2004 IEEE Region 10 Conference, TENCON | |
| dc.title | A 12-bit 150-MHz 1.25-mm2 CMOS DAC | en |
| dc.contributor.institution | School of Physics, Engineering & Computer Science | |
| dc.contributor.institution | Department of Engineering and Technology | |
| dc.contributor.institution | Centre for Engineering Research | |
| dc.contributor.institution | Centre for Future Societies Research | |
| dc.contributor.institution | Communications and Intelligent Systems | |
| rioxxterms.versionofrecord | 10.1109/TENCON.2004.1414913 | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
