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        A flexible VLSI parallel processing system for block-matching motion estimation in low bit-rate video coding applications

        Author
        Xu, D L
        Sotudeh, R
        Attention
        2299/6938
        Abstract
        In this paper, we design a flexible VLSI-based parallel processing system for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the proposed architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.
        Publication date
        1999
        Published in
        Parallel Computation
        Published version
        https://doi.org/10.1007/3-540-49164-3_24
        Other links
        http://hdl.handle.net/2299/6938
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