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        Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm

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        904235.pdf (PDF, 282Kb)
        Author
        He, Y.
        Sun, Y.
        Attention
        2299/7072
        Abstract
        This paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper.
        Publication date
        2001
        Published in
        Procs IEEE Int Symposium on Circuits & Systems
        Published version
        https://doi.org/10.1109/ISCAS.2001.922372
        Other links
        http://hdl.handle.net/2299/7072
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