Instruction scheduling for a superscalar architecture

Collins, R. and Steven, G.B. (1996) Instruction scheduling for a superscalar architecture. UH Computer Science Technical Report . University of Hertfordshire.
Copy

It is increasingly accepted that superscalar processors can only achieve their full performance potential through compile-time instruction scheduling. This paper presents preliminary performance results using a Conditional Group Scheduler which targets the HSA processor model developed at the University of Hertfordshire. In particular, we show that guarded instruction execution improves performance by allowing the processor to squash instructions in the Instruction Buffer before they are issued to functional units and enables the scheduler to delete a significant number of branch instructions.


picture_as_pdf
CSTR+248.pdf

View Download

Atom BibTeX OpenURL ContextObject in Span OpenURL ContextObject Dublin Core MPEG-21 DIDL Data Cite XML EndNote HTML Citation METS MODS RIOXX2 XML Reference Manager Refer ASCII Citation
Export

Downloads