Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems

Number Plate (NP) binarisation and adjustment are very important pre-processing stages in Automatic Number Plate Recognition (ANPR) systems and are used to link the Number Plate Localisation (NPL) and Character segmentation (CS) stages. Successfully linking these two stages will improve the performance of the entire ANPR system. This paper presents two optimised low complexity NP binarisation and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07-0.17ms.