Browsing by Author "Collins, R."

Now showing items 1-5 of 5

    • Developing a simulator for the Hatfield Superscalar processor 

      Collins, R. (University of Hertfordshire, 1993)
      Researchers at the University of Hertfordshire's department of Computer Science are currently investigating the possibility of scheduling code at compile time for a new family of superscalar processors. This project has ...

    • An explicitly declared delayed-branch mechanism for a superscalar architecture 

      Collins, R.; Steven, G.B. (University of Hertfordshire, 1994)
      One of the main obstacles to exploiting the fine-grained parallelism that is available in general-purpose code is the frequency of branches that cause unpredictable changes in the control flow of a program at run-time. ...

    • Instruction scheduling for a superscalar architecture 

      Collins, R.; Steven, G.B. (University of Hertfordshire, 1996)
      It is increasingly accepted that superscalar processors can only achieve their full performance potential through compile-time instruction scheduling. This paper presents preliminary performance results using a Conditional ...

    • An introduction to the Hatfield superscalar architecture 

      Steven, G.B.; Christianson, B.; Collins, R.; Potter, R.; Steven, F.L. (University of Hertfordshire, 1996)
      If a high-performance superscalar processor is to realise its full potential, the complier must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent ...

    • A superscalar architecture to exploit instruction level parallelism 

      Steven, G.B.; Christianson, B.; Collins, R.; Steven, F.L.; Potter, R. (1997-03-17)
      If a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent ...