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        A 90-GHz Asymmetrical Single-Pole Double-Throw Switch with >19.5-dBm 1-dB Compression Point in Transmission Mode Using 55-nm Bulk CMOS Technology

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        ASPDT_TCAS1_final.pdf (PDF, 1Mb)
        Author
        Chen, Lisheng
        Chen, Lang
        Ge, Zeyu
        Sun, Yichuang
        Hamilton, Tara
        Zhu, Xi
        Attention
        2299/25033
        Abstract
        The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2.
        Publication date
        2021-08-25
        Published in
        IEEE Transactions on Circuits and Systems I: Regular Papers
        Published version
        https://doi.org/10.1109/TCSI.2021.3106231
        Other links
        http://hdl.handle.net/2299/25033
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